Memristive Circuit Research Articles

Robust Stabilization of Memristor-based Coupled Neural Networks with Time-varying Delays

The robust stabilization problem of memristor-based coupled neural networks (MNNs) is addressed in this paper. Firstly, the fuzzy model of MNNs is obtained by considering the properties of memristor and corresponding circuit, some predictable assumptions on the boundedness and Lipschitz continuity of activation functions are formulated. Secondly, based on T-S fuzzy theory and Lyapunov-Krasovskii functional method, robust stabilization criteria are derived in form of linear matrix inequalities (LMIs). Finally a numerical example is presented to demonstrate the effectiveness of the proposed robust stabilization criteria, which well supports theoretical results.

Hybrid Circuit of Memristor and Complementary Metal-Oxide-Semiconductor for Defect-Tolerant Spatial Pooling with Boost-Factor Adjustment.

Hierarchical Temporal Memory (HTM) has been known as a software framework to model the brain’s neocortical operation. However, mimicking the brain’s neocortical operation by not software but hardware is more desirable, because the hardware can not only describe the neocortical operation, but can also employ the brain’s architectural advantages. To develop a hybrid circuit of memristor and Complementary Metal-Oxide-Semiconductor (CMOS) for realizing HTM’s spatial pooler (SP) by hardware, memristor defects such as stuck-at-faults and variations should be considered. For solving the defect problem, we first show that the boost-factor adjustment can make HTM’s SP defect-tolerant, because the false activation of defective columns are suppressed. Second, we propose a memristor-CMOS hybrid circuit with the boost-factor adjustment to realize this defect-tolerant SP by hardware. The proposed circuit does not rely on the conventional defect-aware mapping scheme, which cannot avoid the false activation of defective columns. For the Modified subset of National Institute of Standards and Technology (MNIST) vectors, the boost-factor adjusted crossbar with defects = 10% shows a rate loss of only ~0.6%, compared to the ideal crossbar with defects = 0%. On the contrary, the defect-aware mapping without the boost-factor adjustment demonstrates a significant rate loss of ~21.0%. The energy overhead of the boost-factor adjustment is only ~0.05% of the programming energy of memristor synapse crossbar.

Pattern Formation With Locally Active S-Type NbOx Memristors

The main focus of this paper is the evolution of complex behavior in a system of coupled nonlinear memristor circuits depending on the applied coupling conditions. Thereby, the parameter space for the local activity and the edge-of-chaos domain will be determined to enable the emergence of the pattern formation in locally coupled cells according to Chua’s principle. Each cell includes a Niobium oxide-based memristor, which may feature a locally active behavior once it is suitably biased on the negative differential resistance region of its DC current-voltage characteristic. It will be shown that there exists a domain of parameters under which each uncoupled cell may become locally active around a stable bias state. More specifically, under these conditions, the coupled cells are on the edge-of-chaos, and can support the static and dynamic pattern formation. The emergence of such complex spatio-temporal behavior in homogeneous structures is a prerequisite for information processing. The theoretical results are confirmed by measurements as well as by the numerical simulations of the accurate device and circuit models.

Memristive continuous Hopfield neural network circuit for image restoration

Image restoration (IR) methods based on neural network algorithms have shown great success. However, the hardware circuits that can perform real-time IR task with high-effective analog computation are few in the literature. To address such problem, we propose a memristor-based continuous Hopfield neural network (HNN) circuit for processing the IR task in this work. In our circuit, a single memristor crossbar array is used to represent synaptic weights and perform matrix operations. Current feedback operation amplifiers are utilized to achieve integral operation and output function. Given these designs, the proposed circuit can perform continuous recursive operations in parallel and process different optimization problems with the programmability of the memristor array. On the basis of the proposed circuit, binary and greyscale image restorations are conducted through self-organizing network operations, providing a hardware implementation platform for IR tasks. Comparative simulations show the designed HNN circuit provides effective improvements in terms of speed and accuracy compared with software simulation. Moreover, the hardware circuit shows good robustness to memristive variation and input noise.

A third-order memristive Wien-bridge circuit and its integrable deformation

In this paper, a novel passive memristor model and its equivalent circuit model are designed, analysed and realised to investigate the memristor characteristics and their applications in nonlinear circuits. By employing this memristor model, a new third-order memristive Wien bridge is set up. Dynamical behaviours of the system are studied in detail, and multiscroll attractors, coexisting bifurcation modes, coexisting attractors, antimonotonicity and transient chaotic bursting are observed in this system by using theoretical analysis, simulation analysis and circuit experiment. Integrable deformation of the memristive Wien-bridge system is analysed. The circuit experiment is performed by replacing the memristor with its equivalent circuit model in the proposed memristor-based Wien-bridge circuit.

Bursting oscillations and coexisting attractors in a simple memristor-capacitor-based chaotic circuit

The design and analysis of a simple autonomous memristive chaotic circuit are important in theoretical, numerical, and experimental demonstrations of complex dynamics. In this paper, a simple autonomous memristive circuit is implemented, which only consists of an active second-order memristive diode bridge and a capacitor. Based on the available circuit, the mathematical model is established and its symmetry, dissipativity, and equilibrium stability are analyzed. Numerical simulations show that the proposed circuit exhibits complex behaviors of unipolar periodic and chaotic bursting oscillations along with coexisting attractors. It is worth noting that the circuit exhibits such a special bursting behavior previously unobserved in third-order autonomous memristive circuits. Moreover, spectral entropy complexities are calculated to provide an intuitive and effectual method for the circuit parameter configurations. The circuit simulations and hardware experiments verify the theoretical analyses and numerical simulations.

Memristive Circuit Design of Emotional Generation and Evolution Based on Skin-Like Sensory Processor.

Sensory processor in human skin is used for processing and transmitting sensations to the brain, which leads to body actions and emotional responses. In this paper, a memristive circuit of emotional generation and evolution based on skin-like sensory processor is proposed. The circuit includes: first, memristive skin-like sensory processor module; second, emotional generation and evolution module; and third, emotional expression module. The first module consists of four single-memristor skin-like sensory processors, which correspond to process sensations of pain, cold, warm, and tactile. It will automatically return to its initial state if sensory signals disappear. But if sensory signals are much strong, it will not automatically return to initial state unless applied "restoring signal" just like a surgical operation. The second module realizes a conversion mechanism from sensations to emotions using memristor as emotional synapse. Given signals from skin-like sensory processor, the memristance will decrease, which means the extent of emotion will increase, such as more happy. This is the emotional generation. The extent of emotion will be changed if the same sensation is applied to skin-like sensory processor repeatedly, which is the emotional evolution. The third module can show the generated emotions visually. The simulation results in PSPICE show that the proposed circuit can generate and evolve emotions like human beings after processing sensory signals from skin. The proposed circuit can be applied in a perceptual robot platform to realize the conversion from sensations to emotions, enabling the robot to have the ability to sense and process information.

Characteristics Analysis of the Fractional-Order Chaotic Memristive Circuit Based on Chua’s Circuit

In this paper, a new fractional-order memristive circuit is defined based on canonical Chua’s circuit and Voltage-controlled memristor model. The fractional-order chaotic system is solved by conformable Adomian decomposition method (CADM), and the complexity characteristics are analyzed through sample entropy (SampEn) algorithm. The complexity analysis results correspond to the bifurcation diagram and Lyapunov exponential spectrum, which shows that SampEn algorithm can effectively reflects complexity of chaotic system. What’s more, the chaos diagrams of complexity with the two parameters variation and the three parameters variation are analyzed. The numerical simulation result indicates that the system parameters variable complexity can effectively reflect the randomness of the fractional-order chaotic system, and the system has rich dynamical performances. It provides the theoretical guidance and experimental evidence for fractional-order memristive chaotic circuit application in cryptography and secure communication.

An Improved Mapping and Optimization Method for Implication-based Memristive Circuits Using And-Inverter Graph

Any logic operation can be realized in implication-based memristive circuits characterized by low energy consumption and nanometre level size. The synthesis method transforms And-Inverter Graphs (AIGs) representation for logic functions into implication-based networks. It includes a mapping process which converts a cascade of nodes in AIGs to a series of implication gates and detects fan-out nodes simultaneously. An optimized copy process is employed to reduce the delay and area of memristive circuits in occurrence of a fanout node. Experiments are carried out over a benchmark set including 33 functions with input variables from 3 to 41. Experimental results are compared with that from the original algorithm and another Majority-Inverter Graphs (MIG) based mapping method. It shows that the improved algorithm can obtain better performance in latency and area on most of the functions in the test set.

Fractional-order cubic nonlinear flux-controlled memristor: theoretical analysis, numerical calculation and circuit simulation

Many studies have proved that the fractional-order system is more accurate than the integer-order system. The theory of fractional calculus has received extensive attention in many fields. The research on flux-controlled memristor has been carried out for several years; however, fractional-order flux-controlled memristor has not received widespread attention. In light of the theory of fractional calculus, a generalized fractional-order dynamic model of flux-controlled memristor is proposed for the first time in this paper. The mathematical model is established and its characteristics of the pinched hysteresis loops are analyzed by changing the order and the frequency. The specific computational formulas of areas of pinched hysteresis loops are given. The equivalent circuit of the fractional-order flux-controlled memristor is constructed, and circuit simulations are given to illustrate the effectiveness of theoretical analysis and numerical calculation. In this study, the flux-controlled memristor model is extended to the fractional-order model that is closer to the real device, and the analysis method of areas of pinched hysteresis loops is further expanded.

A Demonstration of Implication Logic Based on Volatile (Diffusive) Memristors

Implication logic gates that are based on volatile memristors are demonstrated experimentally with the use of relay-based volatile memristor emulators of an original design. The fabricated logic circuit involves two volatile memristors and it is capable of performing four fundamental logic functions (two types of material implication and the negations thereof). Moreover, current-voltage characteristics of individual emulators are recorded and self-sustained oscillations in a resistor-volatile memristor circuit are found. The developed emulator offers a great potential for memristive circuit experiments because of its simplicity, similarity of response with volatile memristors, and low cost. Our findings, which are based on emulators, can easily be reproduced with physical volatile memristors and, thus, open up possibilities for emerging in-memory computing architectures.

Neuromorphic Computing: Designed Memristor Circuit for Self‐Limited Analog Switching and its Application to a Memristive Neural Network (Adv. Electron. Mater. 6/2019)

In article number 1800740, H. Song et al. propose an analog data-programming method for memristors via in-memory operation in a crossbar array. Analog data can be transferred from a selected reference resistor cell to the target memristor cell by appropriate voltage clocking. Such data transfer can be triggered at any location in the array accurately and quickly; optimization of the design gives a characteristic error of just 2.95%. Their method is then applied to program a memristive neural network and the error is confirmed to be negligible, suggesting this setup can be used in neuromorphic computing applications.

Electronically tunable memristor based on VDCC

In this study, a simple memristor circuit using only one Voltage Differencing Current Conveyor (VDCC), two PMOS transistors and one grounded capacitor, is designed. The presented memristor exhibits electronically controllable characteristics, which are superior to its counterparts. Both the memductance value and the operating frequency can be electronically tuned through voltage sources. The proposed memristor, which occupies 42.2 µm × 27.5 µm area excluding the area of the capacitor, is laid by using Cadence Environment using TSMC 0.18 µm process parameters. In addition, the proposed memristor is implemented by using discrete circuit elements on the breadboard and detailed analyses are given by changing the values of the discrete circuit elements. All results are compatible with the previous studies.

Transient dynamics of pulse-driven memristors in the presence of a stable fixed point

Some memristors are quite interesting from the point of view of dynamical systems. When driven by narrow pulses of alternating polarities, their dynamics has a stable fixed point, which may be useful for future applications. We study the transient dynamics of two types of memristors characterized by a stable fixed point using a time-averaged evolution equation. Time-averaged trajectories of the Biolek window function memristor and resistor-threshold type memristor circuit (an effective memristor) are determined analytically, and the times of relaxation to the stable fixed point are found. Our analytical results are in perfect agreement with the results of numerical simulations.

Phase synchronization and lock between memristive circuits under field coupling

The dynamics of nonlinear circuits becomes dependent on the initials setting when memristor is included to design nonlinear circuits, and this memristive circuits can cause distinct transition between periodical and chaotic states by resetting the initial-dependent variables even all the parameters are fixed. A memristive circuit is used to investigate the synchronization stability when the resistor, capacitor, induction coil is applied to connect two identical circuits, respectively. For resistor-based voltage coupling, single channel coupling can realize phase lock even the resistor has to consume more Joule heat with the increase of coupling intensity. In case of capacitor coupling, continuous pump of electric field energy in the coupling capacitor can trigger time-varying electric field and then the phase errors between two circuits are locked. When induction coil is applied to couple two circuits, time-varying magnetic field is triggered to save field energy pumped from the two coupling circuits and then phase errors can also be stabilized. The three kinds of coupling between nonlinear circuits can modulate synchronization via continuous energy exchange and pumping. The coupling resistor just consumes Joule heat while capacitor and induction coil coupling can pump and save field energy and it provide another scheme as field coupling.

Flux–Charge Analysis of Two-Memristor-Based Chua's Circuit: Dimensionality Decreasing Model for Detecting Extreme Multistability

In this paper, from a new perspective of flux and charge, we present in-depth analyses of two ideal memristor emulators and the fifth-order memristive Chua's circuit constructed based on them. The constitutive flux–charge relations of the two adopted memristor emulators are first formulated, and their initial-dependent characteristics are numerically revealed and experimentally verified. Thereafter, with these two constitutive relations, a third-order dimensionality decreasing flux–charge model for the fifth-order memristive Chua's circuit is constructed, in which five extra constant system parameters are introduced to indicate the initial states of the five dynamic elements. Numerical simulations confirm that this newly constructed model possesses several determined equilibria and maintains the initial-dependent dynamics of the original voltage–current model. Thus, the complex and sensitive initial state-related extreme multistability phenomenon can be deeply explored through theoretical analyses and hardware measurements. It is demonstrated that the sensitive extreme multistability phenomenon becomes detectable in the flux–charge domain, which is efficient for exploring the inner mechanisms and further seeking possible applications of this special phenomenon.

Hidden extreme multistability and dimensionality reduction analysis for an improved non-autonomous memristive FitzHugh–Nagumo circuit

Due to the introduction of ideal memristors, extreme multistability has been found in many autonomous memristive circuits. However, such extreme multistability has not yet been reported in a non-autonomous memristive circuit. To this end, this paper presents an improved non-autonomous memristive FitzHugh–Nagumo circuit that possesses a smooth hyperbolic tangent memductance nonlinearity, from which coexisting infinitely many attractors are obtained. By utilizing voltage–current circuit model, a three-dimensional non-autonomous dynamical model is established, based on which the initial-dependent dynamics is explored by numerical plots and extreme multistability is thereby exhibited. To confirm that the improved non-autonomous memristive circuit operates in hidden oscillating patterns, an accurate two-dimensional non-autonomous dimensionality reduction model with initial-related parameters is further built by using incremental integral transformation, upon which stability analysis and bifurcation behaviors are elaborated. Because the equilibrium state of the dimensionality reduction model is always a stable node-focus, hidden extreme multistability with coexisting infinitely many attractors is truly confirmed. Finally, PSIM circuit simulations validate the initial-related hidden dynamical behaviors.

Analysis of Memory Matrices with HfO2 Memristors in a PSpice Environment

The investigation of new memory circuits is very important for the development of future generations’ non-volatile and Random Access Memories (RAM) memories and modern schemes for in-memory calculations. The purpose of the present research is to propose a detailed analysis of passive and hybrid memristor-based memory crossbars with separating metal oxide semiconductor (MOS) transistors. The considered memristors are based on HfO2. The transistors are applied to eliminate the parasitic paths in the schemes. For simulations, a previously proposed strongly nonlinear modified window function by the author together with a physical nonlinear memristor model is used. The considered model is adjusted according to the experimental i–v relationship of HfO2 memristors. The i–v relationship obtained by the simulation is successfully fitted to the respective relationship derived by physical measurements. A good coincidence between these characteristics is established. Several basic window functions are also applied for comparison to the corresponding results. The proposed model is analyzed in Personal Simulation Program with Integrated Circuit Emphasis (PSpice) and it is also used for simulation of a 5 × 5 fragment of a memristor memory crossbar with isolating transistors and for the analysis of a 6 × 6 passive memory matrix. The investigated matrices are simulated for writing, reading, and erasing information. It is established that the model proposed could be used for simulations of complex memristor circuits.

Designed Memristor Circuit for Self‐Limited Analog Switching and its Application to a Memristive Neural Network

AbstractAnalog memristors enable compact neuromorphic computing with low power consumption. One of the issues with the technology is slow precise analog data programming. In this study, a novel analog data programming method utilizing a self‐limited set switching is proposed. The method can transfer any resistance values from reference resistors to the target memristor accurately inside a crossbar array by performing an appropriate voltage clocking. An ideal memristor model based on the method is proposed and a Ti‐doped NbOx charge trap memristor is evaluated as a promising candidate for applications. The characteristic error of the Ti‐doped NbOx memristor device is about 5% on average, compared to the ideal memristor, and configuring optimum parallel resistors in the circuit further improves this to 2.95%. The method is then applied to program a memristive neural network and this error is confirmed negligible; thus the proposed method is viable.

Analysis, Control and FPGA Implementation of a Fractional-Order Modified Shinriki Circuit

In this paper, we introduce a novel integer-order memristor-modified Shinriki circuit (MMSC). We investigate the dynamic properties of the MMSC system and the existence of chaos is proved with positive largest Lyapunov exponent. Bifurcation plots are derived to analyze the parameter dependence of the MMSC system. The fractional-order model of the MMSC system (FOMMSC) is derived and the bifurcation analysis of the FOMMSC system with the fractional orders is carried out. Fractional-order adaptive sliding-mode controllers (FOASMCs) and genetically optimized PID controllers are designed to synchronize identical FOMMSC systems with unknown parameters. Numerical simulations are conducted to validate the theoretical results. FPGA implementation of the FOASMC controllers is presented to show that the proposed control algorithm is hardware realizable. MMSC has trigonometric functions which make the system more complex and the optimization and synchronization of such systems in the integer order itself are harder, so the paper does the same in fractional order. The proposed system is a memristive circuit which can show special features such as multistability, hyperchaos, and multiscroll attractor. Such a system with these features is very rare in the literature.