An Improved Mapping and Optimization Method for Implication-based Memristive Circuits Using And-Inverter Graph

Abstract

Any logic operation can be realized in implication-based memristive circuits characterized by low energy consumption and nanometre level size. The synthesis method transforms And-Inverter Graphs (AIGs) representation for logic functions into implication-based networks. It includes a mapping process which converts a cascade of nodes in AIGs to a series of implication gates and detects fan-out nodes simultaneously. An optimized copy process is employed to reduce the delay and area of memristive circuits in occurrence of a fanout node. Experiments are carried out over a benchmark set including 33 functions with input variables from 3 to 41. Experimental results are compared with that from the original algorithm and another Majority-Inverter Graphs (MIG) based mapping method. It shows that the improved algorithm can obtain better performance in latency and area on most of the functions in the test set.