Memristor Array Research Articles

Ni Single-Atoms Based Memristors with Ultrafast Speed and Ultralong Data Retention.

Memristor with low-power, high density, and scalability fulfills the requirements of the applications of the new computing system beyond Moore's law. However, there are still nonideal device characteristics observed in the memristor to be solved. The important observation is that retention and speed are correlated parameters of memristor with trade off against each other. The delicately modulating distribution and trapping level of defects in electron migration-based memristor is expected to provide a compromise method to address the contradictory issue of improving both switching speed and retention capability. Here, high-performance memristor based on the structure of ITO/Ni single-atoms (NiSAs/N-C)/Polyvinyl pyrrolidone (PVP)/Au is reported. By utilizing well-distributed trapping sites , small tunneling barriers/distance and high charging energy, the memristor with an ultrafast switching speed of 100ns, ultralong retention capability of 106 s, a low set voltage (Vset ) of ≈0.7V, a substantial ON/OFF ration of 103 , and low spatial variation in cycle-to-cycle (500 cycles) and device-to-device characteristics (128 devices) is demonstrated. On the premise of preserving the strengths of a fast switching speed, this memristor exhibits ultralong retention capability comparable to the commercialized flash memory. Finally, a memristor ratioed logic-based combinational memristor array to realize the one-bit full adder is further implemented.

3D Vertical Self-Rectifying Memristor Arrays With Split-Cell Structure, Large Nonlinearity (>104) and fJ-Level Switching Energy

3D Vertical Self-Rectifying Memristor Arrays With Split-Cell Structure, Large Nonlinearity (>10⁴) and fJ-Level Switching Energy

Monolithic 3D integration of 2D materials-based electronics towards ultimate edge computing solutions.

Three-dimensional (3D) hetero-integration technology is poised to revolutionize the field of electronics by stacking functional layers vertically, thereby creating novel 3D circuity architectures with high integration density and unparalleled multifunctionality. However, the conventional 3D integration technique involves complex wafer processing and intricate interlayer wiring. Here we demonstrate monolithic 3D integration of two-dimensional, material-based artificial intelligence (AI)-processing hardware with ultimate integrability and multifunctionality. A total of six layers of transistor and memristor arrays were vertically integrated into a 3D nanosystem to perform AI tasks, by peeling and stacking of AI processing layers made from bottom-up synthesized two-dimensional materials. This fully monolithic-3D-integrated AI system substantially reduces processing time, voltage drops, latency and footprint due to its densely packed AI processing layers with dense interlayer connectivity. The successful demonstration of this monolithic-3D-integrated AI system will not only provide a material-level solution for hetero-integration of electronics, but also pave the way for unprecedented multifunctional computing hardware with ultimate parallelism.

Direct Visualization of Charge Migration in Bilayer Tantalum Oxide Films by Multimodal Imaging

AbstractInspired by biological neuromorphic computing, artificial neural networks based on crossbar arrays of bilayer tantalum oxide memristors have shown to be promising alternatives to conventional complementary metal‐oxide‐semiconductor (CMOS) architectures. In order to understand the driving mechanism in these oxide systems, tantalum oxide films are resistively switched by conductive atomic force microscopy (C‐AFM), and subsequently imaged by kelvin probe force microscopy (KPFM) and spatially resolved time‐of‐flight secondary ion mass spectrometry (ToF‐SIMS). These workflows enable induction and analysis of the resistive switching mechanism as well as control over the resistively switched region of the film. In this work it is shown that the resistive switching mechanism is driven by both current and electric field effects. Reversible oxygen motion is enabled by applying low (<1 V) electric fields, while high electric fields generate irreversible breakdown of the material (>1 V). Fully understanding oxygen motion and electrical effects in bilayer oxide memristor systems is a fundamental step toward the adoption of memristors as a neuromorphic computing technology.

In-Memory Computing Circuit Implementation of Complex-Valued Hopfield Neural Network for Efficient Portrait Restoration

Complex-valued neural networks have better optimization capabilities, stronger robustness and richer characterization capabilities compared with real-valued neural networks, which has achieved good results in the field of portrait restoration. However, there is almost no circuit implementation of complex-valued neural networks. Based on this, this paper proposes an in-memory computing circuit implementation of complex-valued Hopfield neural network (CHNN) for the first time, which provides a highly accurate and efficient processing circuit for portrait restoration. Firstly, a new memristive array is proposed, which can realize parallel complex-valued multiplication and complex-valued vector-matrix multiplication. On the basis, a CHNN circuit that can perform large-scale recursive computations is designed. Due to the characteristics of in-memory computation, the computation speed and robustness have been improved when realizing portrait restoration. Different portrait restoration scenarios can be realized based on the programmability of the memristive array. Pspice simulation results show that the recovery speed of CHNN can reach the level of 0.1 ms, and the accuracy can reach above 97.00%. Robustness analysis shows that the circuit can tolerate a certain degree of programming error and has strong anti-noise performance.

Wafer‐Scale Memristor Array Based on Aligned Grain Boundaries of 2D Molybdenum Ditelluride for Application to Artificial Synapses

Abstract2D materials have attracted attention in the field of neuromorphic computing applications, demonstrating the potential for their use in low‐power synaptic devices at the atomic scale. However, synthetic 2D materials contain randomly distributed intrinsic defects and exhibit a stochasitc forming process, which results in variability of switching voltages, times, and stat resistances, as well as poor synaptic plasticity. Here, this work reports the wafer‐scale synthesis of highly polycrystalline semiconducting 2H‐phase molybdenum ditelluride (2H‐MoTe2) and its use for fabricating crossbar arrays of memristors. The 2H‐MoTe2 films contain small grains (≈30 nm) separated by vertically aligned grain boundaries (GBs). These aligned GBs provide confined diffusion paths for metal ions filtration (from the electrodes), resulting in reliable resistive switching (RS) due to conductive filament confinement. As a result, the polycrystalline 2H‐MoTe2 memristors shows improvement in the RS uniformity and stable multilevel resistance states, small cycle‐to‐cycle variation (<8.3%), high yield (>83.7%), and long retention times (>104 s). Finally, 2H‐MoTe2 memristors show linear analog synaptic plasticity under more than 2500 repeatable pulses and a simulation‐based learning accuracy of 96.05% for image classification, which is the first analog synapse behavior reported for 2D MoTe2 based memristors.

A Hybrid Weight Quantization Strategy for Memristive Neural Networks

Due to the ability to store data and process information, the memristor-based neuromorphic system has attracted extensive attention. Its efficient parallel computing approach allows it to implement neural networks in hardware. However, due to the limitation of the range of memristor conductance, it is difficult to represent high-precision weights in memristive neural network. During the off-chip learning, it is crucial to find an efficient weight quantization scheme and map it to the memristor array. Therefore, a hybrid weight quantization strategy that combines uniform and non-uniform quantization is proposed to overcome these problems. Specifically, the curve fitting of pulse modulation for tantalum oxide-based memristor is carried out, and the mapping rules of weights are proposed to simplify the process of reading verification. Furthermore, the hybrid quantization strategy is proposed and applied to a multilayer perceptron and a convolutional neural network, respectively. The effectiveness and robustness of the hybrid quantization scheme are verified in the MNIST dataset. Experiments show that the proposed hybrid quantization scheme can achieve 99.26% accuracy at 4 bits and tolerate 20% noise interference. The simulation results in this paper also provide an effective solution for the hardware implementation of memristive neural networks.

A novel brain-inspired hierarchical perception-association circuit based on memristor arrays

In the brain, primary sensory cells can efficiently perceive multimodal stimuli, and then associative memory cells perform an advanced bidirectional associative memory function with perceived information. Here, a brain-inspired hierarchical perception-association circuit based on memristor arrays is proposed. Firstly, a memristive reservoir computing circuit is designed to simulate a low-level perceptual function, which mainly comprises dynamic analog reservoirs, memristor arrays, and analog integrators, enabling efficient spatio-temporal information processing. Secondly, a spiking bidirectional associative memory memristive circuit, as the core of the whole circuit, is proposed to mimic a high-level associative function, which mainly consists of memristor arrays, current amplifiers, and leaky integrate-and-fire neuron circuits, implementing multimodal associative learning. The simulation results in LTspice show that the modified neuron circuit exhibits 66× improvement in energy efficiency, and the proposed circuit can precisely perform the letter association and vision–audio association tasks in a spiking fashion with an average firing energy consumption of 230 pJ/spike, which has a great potential to be embedded in mobile robotic platforms.

A Brain-Inspired Hardware Architecture for Evolutionary Algorithms Based on Memristive Arrays

Brain-inspired computing takes inspiration from the brain to create energy-efficient hardware systems for information processing, capable of performing highly sophisticated tasks. Systems built with emerging electronics, such as memristive devices, can achieve gains in speed and energy by mimicking the distributed topology of the brain. In this work, a brain-inspired hardware architecture for evolutionary algorithms is proposed based on memristive arrays, which can realize sparse and approximate computing as a result of the parallel analog computing characteristic of the memristive arrays. On this basis, an efficient evolvable brain-inspired hardware system is implemented. We experimentally show that the approach can offer at least a four orders of magnitude speed improvement. We also use experimentally grounded simulations to explore fault tolerance and different parameter settings in the implemented hardware system. The experimental results show that the evolvable hardware system, implemented based on the proposed hardware architecture, can continuously evolve toward a better system even if there are failures or parameter changes in the memristive arrays, demonstrating that the proposed hardware architecture has good adaptability and fault tolerance.

Research on the construction method of neural network model based on memristors

Abstract With the continuous development of neural networks, the hardware requirements are getting higher and higher, and the emergence of memristors is expected to optimize this challenge. In this paper, by studying the inter-mapping relationship between memristor arrays and neural networks, a memristor-based convolutional neural network circuit module is designed, a binarization method is used to quantize the neural network, an acceleration module is constructed based on multiple computational arrays, and an additive tree is used to accumulate the intermediate results of the output values of multiple computational units. Simulation experiments were conducted with the help of simulation software to compare and analyze the memristor-based CNN with other neural networks. Compared with LSTM, RNN, and ELM, the accuracy of the memristor-based CNN is 4.17%, 7.48%, and 2.01% higher compared to other neural networks, respectively. In the performance analysis, the recognition rate of the memristor CNN is almost unaffected by the programming error and still achieves a recognition rate close to 98% in the best case. This study provides a new idea for implementing and applying convolutional neural networks in memristor arrays, which is expected to promote the further development of memristor neuromorphic computing.

Effect of memristor’s potentiation-depression curves peculiarities in the convergence of physical perceptrons

Neuromorphic computing aims to emulate the architecture and information processing mechanisms of the mammalian brain. This includes the implementation by hardware of neural networks. Oxide-based memristor arrays with cross-bar architecture appear as a possible physical implementation of neural networks. In this paper, we obtain experimental potentiation-depression (P-D) curves on different manganite-based memristive systems and simulate the learning process of perceptrons for character recognition. We analyze how the specific characteristics of the P-D curves affect the convergence time -characterized by the EPOCHs-to-convergence (ETC) parameter- of the network. Our work shows that ETC is reduced for systems displaying P-D curves with relatively low granularity and non-linear and asymmetric response. In addition, we also show that noise injection during the synaptic weight actualization further reduces the ETC. The results obtained here are expected to contribute to the optimization of hardware neural networks based on memristors cross-bar arrays.

Tunable voltage polarity-dependent resistive switching characteristics by interface energy barrier modulation in ceria-based bilayer memristors for neuromorphic computing

Synaptic characteristics with tunable dependence on the voltage polarity are demonstrated in ceria (CeO2) and Gd-doped ceria (GDC) bilayer memristors with respect to their stacking orders. Both Pt/GDC/CeO2/Pt and Pt/CeO2/GDC/Pt memristors with different oxide stacking orders exhibit analog, linear, and symmetric synaptic weights for potentiation and depression, paired-pulse facilitation, and short- and long-term plasticity (STP and LTP, respectively). Potentiation and depression behaviors are highly linear and symmetric thanks to the stacking of more oxygen-deficient GDC layer with CeO2, which facilitates the redistribution of oxygen vacancies for analog resistance change. These memristors have opposite dependence of synaptic weight updates on the polarity of potentiation and depression voltages for the stacking order of CeO2 and GDC, which are consistently interpreted by voltage-driven energy barrier modulation at the interface between CeO2 and GDC or with Pt electrodes via oxygen vacancy redistribution. Recognition simulation with modified handwritten digits patterns using a two-layer perceptron neural network exhibits accuracy of approximately 88% with achieved dynamic range, linearity, symmetry, and precision states. These synaptic characteristics are also demonstrated in a 32 × 32 crossbar array of GDC-top memristors. This verifies the potential of bilayer memristors for application in artificial synapse networks in neuromorphic computing systems.

Flexible, Transparent, and Wafer-Scale Artificial Synapse Array Based on TiOx /Ti3 C2 Tx Film for Neuromorphic Computing.

A high-density neuromorphic computing memristor array based on 2Dmaterials paves the way for next-generation information-processing components and in-memory computing systems. However, the traditional 2D-materials-based memristor devices suffer from poor flexibility and opacity, which hinders the application of memristors in flexible electronics. Here, a flexible artificial synapse array based on TiOx /Ti3 C2 Tx film is fabricated by a convenient and energy-efficient solution-processing technique, which realizes high transmittance (≈90%) and oxidation resistance (>30 days). The TiOx /Ti3 C2 Tx memristor shows low device-to-device variability, long memory retention and endurance, a high ON/OFF ratio, and fundamental synaptic behavior. Furthermore, satisfactory flexibility (R = 1.0mm) and mechanical endurance (104 bending cycles) of the TiOx /Ti3 C2 Tx memristor are achieved, which is superior to other film memristors prepared by chemical vapor deposition. In addition, high-precision (>96.44%) MNIST handwritten digits recognition classification simulation indicates that the TiOx /Ti3 C2 Tx artificial synapse array holds promise for future neuromorphic computing applications, and provides excellent high-density neuron circuits for new flexible intelligent electronic equipment.

Highly Reliable Textile-Type Memristor by Designing Aligned Nanochannels.

Information-processing devices are the core components of modern electronics. Integrating them into textiles is the indispensable demand for electronic textiles to form close-loop functional systems. Memristors with cross-bar configuration are regarded as promising building blocks to design woven information-processing devices that seamlessly unify with textiles. However, the memristors always suffer from severe temporal and spatial variations due to the random growth of conductive filaments during filamentary switching processes. Here, inspired by the ion nanochannels across synaptic membranes, we report a highly reliable textile-type memristor made of Pt/CuZnS memristive fiber with aligned nanochannels, showing small set voltage variation (<5.6%) under ultralow set voltage (∼0.089V), high on/off ratio (∼106 ) and low power consumption (0.1 nW). Experimental evidences indicate that nanochannels with abundant active S defects could anchor silver ions and confine their migrations to form orderly and efficient conductive filaments. Such memristive performances enable the resultant textile-type memristor array to have high device-to-device uniformity and process complex physiological data like brainwave signals with high recognition accuracy (95%). Our textile-type memristor arrays are mechanically durable to withstand hundreds of bending and sliding deformations, and seamlessly unified with sensing, power-supplying and displaying textiles/fibers to form all-textile integrated electronic systems for new-generation human-machine interactions. This article is protected by copyright. All rights reserved.

Dot-product computation and logistic regression with 2D hexagonal-boron nitride (h-BN) memristor arrays

This work reports on the hardware implementation of analog dot-product operation on arrays of two-dimensional (2D) hexagonal boron nitride (h-BN) memristors. This extends beyond previous work that studied isolated device characteristics towards the application of analog neural network accelerators based on 2D memristor arrays. The wafer-level fabrication of the memristor arrays is enabled by large-area transfer of CVD-grown few-layer (8 layers) h-BN films. Individual devices achieve an on/off ratio of >10, low voltage operation (∼0.5 V set/V reset), good endurance (>6000 programming steps), and good retention (>104 s). The dot-product operation shows excellent linearity and repeatability, with low read energy consumption (∼200 aJ to 20 fJ per operation), with minimal error and deviation over various measurement cycles. Moreover, we present the implementation of a stochastic logistic regression algorithm in 2D h-BN memristor hardware for the classification of noisy images. The promising resistive switching characteristics, performance of dot-product computation, and successful demonstration of logistic regression in h-BN memristors signify an important step towards the integration of 2D materials for next-generation neuromorphic computing systems.

Sparse matrix multiplication in a record-low power self-rectifying memristor array for scientific computing.

Memristor-enabled in-memory computing provides an unconventional computing paradigm to surpass the energy efficiency of von Neumann computers. Owing to the limitation of the computing mechanism, while the crossbar structure is desirable for dense computation, the system's energy and area efficiency degrade substantially in performing sparse computation tasks, such as scientific computing. In this work, we report a high-efficiency in-memory sparse computing system based on a self-rectifying memristor array. This system originates from an analog computing mechanism that is motivated by the device's self-rectifying nature, which can achieve an overall performance of ~97 to ~11 TOPS/W for 2- to 8-bit sparse computation when processing practical scientific computing tasks. Compared to previous in-memory computing system, this work provides over 85 times improvement in energy efficiency with an approximately 340 times reduction in hardware overhead. This work can pave the road toward a highly efficient in-memory computing platform for high-performance computing.

Emulation of auditory senses depending on chaotic dynamics of threshold switching memristor

AbstractEmulating the auditory sense is a significant challenge in terms of both integration and energy consumption for handling complicated spatiotemporal information. Here, we demonstrate how to utilize the chaotic dynamics of a threshold switching memristor, which usually acts as a leaky integrate and fire neuron in the neuromorphic network, to encode the frequency and amplitude in auditory information. We fabricate a Pd/Nb/NbOx/Nb/Pd memristor dominated by the Poole–Frankel conduction mechanism, set its state at the edge of chaos, and stimulate it using periodic perturbations. The memristor's responses to the perturbation frequencies can be categorized into three zones. Two are phase locking with linear phase–frequency relationships, and one has a hyperbolic spike number–frequency relationship. The memristor system also enables intensity coding and tonotopy by modulating the response spikes in either the locked phase or spike number. Based on the emulation of these two features, the memristor system demonstrates sound location and frequency mixing. Our study suggests a novel routine for handling the auditory and visual senses using threshold‐switching memristor arrays to enhance the efficiency of neuromorphic networks.image

Neuromorphic Computing Based on CMOS-Integrated Memristive Arrays: Current State and Perspectives

Neuromorphic Computing Based on CMOS-Integrated Memristive Arrays: Current State and Perspectives

Progress on Memristor-Based Analog Logic Operation

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

Internal ion transport in ionic 2D CuInP2S6 enabling multi-state neuromorphic computing with low operation current

Memristor-based neuromorphic computing is promising for artificial intelligence. However, most of the reported memristors have limited linear computing states and consume large operation energy which hinder their applications. Herein, we report a memristor based on ionic two-dimensional CuInP2S6 (2D CIPS), in which up to 1350 linear conductance states are achieved by controlling the migration of internal Cu ions in CIPS. In addition, the device shows a low operation current of ∼100 pA. Cu ions are proven to move along the electric field by in-situ scanning electron microscopy and energy dispersive spectroscopy measurements. Furthermore, complex signal transport among multiple neurons in the brain is imitated by 2D CIPS-based memristor arrays. Our results offer a new platform to fabricate high-performance memristors based on ion transport in 2D materials for neuromorphic computing.