Memristive Circuit Research Articles

Testability design of memristive digital circuits based on Knowm memristor

A multi-function memristive logic test unit based on Knowm memristor is designed and implemented to the memristive digital circuits testability design in this article. The single fault memristive digital circuit is analyzed, Boolean difference algorithm is applied to the memristive digital circuits to generate test patterns and determine the location of the fault nodes. The multi-function memristive logic test unit can realize different functions, combining Boolean difference to solve the problem of uncertain faults with the same test patterns, and improve the controllability and observability of memristive digital circuits. It is a new exploration in testability design of memristive digital circuits, which provides new ideas and development directions, and lays a foundation for the research on the testability design of multi fault memristor digital circuits.

Neuromorphic Circuit Implementation of Operant Conditioning Based on Emotion Generation and Modulation

In this work, an operant conditioning (OC) model and memristive circuit implementation based on emotion generation and modulation is proposed, which is inspired by neural and psychological mechanisms to simulate human behavioral decisions guided by reinforcers and emotional changes during interaction with dynamically changing environments. The OC model consists of four main modules which are the cue-synapse-action module, the reward and punishment value systems, and the emotion system. Under four conditions of reward appearance or termination, and punishment appearance or termination, the memristive circuit designed according to the OC model can realize the process of exploration, acquisition, extinction, and recovery of OC (external phenomena), and also reflect the process of change of value signals and emotion signals (internal states). In addition, the phenomena of reward fatigue and punishment adaptation are considered so that value and emotion signals gradually diminish with the repetition of invariant reinforcers. The neuromorphic circuit is verified to have good robustness and device tolerance. This work enables multi-timescale OC tasks and is expected to be applied in an emotionally intelligent robot platform to achieve humanoid functions such as real-time dynamic decision-making for interaction with the environment and emotional companionship.

Dynamical memristive neural networks and associative self-learning architectures using biomimetic devices.

While there is an abundance of research on neural networks that are "inspired" by the brain, few mimic the critical temporal compute features that allow the brain to efficiently perform complex computations. Even fewer methods emulate the heterogeneity of learning produced by biological neurons. Memory devices, such as memristors, are also investigated for their potential to implement neuronal functions in electronic hardware. However, memristors in computing architectures typically operate as non-volatile memories, either as storage or as the weights in a multiply-and-accumulate function that requires direct access to manipulate memristance via a costly learning algorithm. Hence, the integration of memristors into architectures as time-dependent computational units is studied, starting with the development of a compact and versatile mathematical model that is capable of emulating flux-linkage controlled analog (FLCA) memristors and their unique temporal characteristics. The proposed model, which is validated against experimental FLCA LixNbO2 intercalation devices, is used to create memristive circuits that mimic neuronal behavior such as desensitization, paired-pulse facilitation, and spike-timing-dependent plasticity. The model is used to demonstrate building blocks of biomimetic learning via dynamical memristive circuits that implement biomimetic learning rules in a self-training neural network, with dynamical memristive weights that are capable of associative lifelong learning. Successful training of the dynamical memristive neural network to perform image classification of handwritten digits is shown, including lifelong learning by having the dynamical memristive network relearn different characters in succession. An analog computing architecture that learns to associate input-to-input correlations is also introduced, with examples demonstrating image classification and pattern recognition without convolution. The biomimetic functions shown in this paper result from fully ion-driven memristive circuits devoid of integrating capacitors and thus are instructive for exploiting the immense potential of memristive technology for neuromorphic computation in hardware and allowing a common architecture to be applied to a wide range of learning rules, including STDP, magnitude, frequency, and pulse shape among others, to enable an inorganic implementation of the complex heterogeneity of biological neural systems.

Picosecond Time‐Scale Resistive Switching Monitored in Real‐Time

AbstractThe resistance state of filamentary memristors can be tuned by relocating only a few atoms at interatomic distances in the active region of a conducting filament. Thereby the technology holds promise not only in its ultimate downscaling potential and energy efficiency but also in unprecedented speed. Yet, the breakthrough in high‐frequency applications still requires the clarification of the dominant mechanisms and inherent limitations of ultra‐fast resistive switching. Here bipolar, multilevel resistive switchings are investigated in tantalum pentoxide based memristors with picosecond time resolution. Cyclic resistive switching operation due to 20 ps long voltage pulses of alternating polarity are experimentally demonstrated. The analysis of the real‐time response of the memristor reveals that the set switching can take place at the picosecond time‐scale where it is only compromised by the bandwidth limitations of the experimental setup. In contrast, the completion of the reset transitions significantly exceeds the duration of the ultra‐short voltage bias, demonstrating the dominant role of thermal diffusion and underlining the importance of dedicated thermal engineering for future high‐frequency memristor circuit applications.

Efficient Spectral Graph Convolutional Network Deployment on Memristive Crossbars

Graph Neural Networks (GNNs) have attracted increasing research interest for their remarkable capability to model graph-structured knowledge. However, GNNs suffer from intensive data exchange and poor data locality, which will cause critical performance and energy bottlenecks under conventional complementary metal oxide semiconductor (CMOS)-based von-Neumann computing architectures (graphics processing unit (GPU), central processing unit (CPU)) for the “Memory Wall” issue. Fortunately, memristive crossbar-based computation has emerged as one of the most promising neuromorphic computing architectures, which has been widely studied as the computing platform for convolutional neural network (CNNs), recurrent neural network (RNNs), spiking neural network (SNNs), etc. This paper proposes the deployment of spectral graph convolutional networks (GCNs) on memristive crossbars. Further, based on the structure of GCNs (extremely high sparsity and unbalanced non-zero data distribution) and the neuromorphic characteristics of memristive crossbar circuit, we propose the acceleration method that consists of Sparse Laplace Matrix Reordering and Diagonal Block Matrix Multiplication. The simulated experiment on memristor crossbars achieves 90.3% overall accuracy on the supervised learning graph dataset (QM7), and compared with the original computation, the proposed acceleration computing framework (with half-size diagonal blocks) achieves a 27.3% reduction of memristor number. Additionally, on the unsupervised learning dataset (Karate club), our method shows no loss of accuracy with half-size diagonal block mapping and reaches a 32.2% reduction of memristor number.

CMOS-Based Memristor Emulator Circuits for Low-Power Edge-Computing Applications

In this paper, an optimized memristor emulator circuit is designed, by using nine MOSFET transistors and a ground capacitor. Our area- and power-optimized emulator circuit can be used for basic data storage and processing at the monitoring edge, in real-time applications. The memristor shows a nonlinear voltage–current relationship, but no multiplier circuit provides the memristor’s nonlinear characteristics. As a result, the proposed memristor emulator has a very low chip area. The memristor circuit is designed in LTSpice, using 16 nm and 45 nm CMOS technology parameters, and the operating voltage is ±0.9 V. In this research, the theoretical derivations are validated using the simulated results of the memristor emulator circuit using different frequencies, capacitors, and input voltages in SPICE simulations.

Locally Active Memristor with Variable Parameters and Its Oscillation Circuit

This paper designs a locally active memristor with two variable parameters based on Chua’s unfolding theorem. The dynamical behavior of the memristor is analyzed by employing pinched hysteresis loop, power-off plot (POP), DC V–I curve, small-signal analysis, and edge-of-chaos theory. It is found that the proposed memristor exhibits nonvolatile and bistable behaviors because of coexisting pinched hysteresis loops. And the variable parameters can realize the rotation of the coexisting pinched hysteresis loops, regulate the range of the locally active region and even transform the shape of the DC V–I curve into S-type or N-type. Furthermore, a simple oscillation circuit is constructed by connecting this locally active memristor with an inductor, a capacitor, a resistance, and a bias voltage. It is shown by analysis that the memristive circuit can generate complex nonlinear dynamics such as multiscroll attractor, initial condition-based dynamics switching, transient phenomenon with the same dynamical state but different offsets and amplitudes, and symmetric coexisting attractors. The measurement observed from the implementation circuit further verifies the numerical results of the oscillation circuit.

From memristive devices to neuromorphic systems

Progress in hardware and algorithms for artificial intelligence (AI) has ushered in large machine learning models and various applications impacting our everyday lives. However, today's AI, mainly artificial neural networks, still cannot compete with human brains because of two major issues: the high energy consumption of the hardware running AI models and the lack of ability to generalize knowledge and self-adapt to changes. Neuromorphic systems built upon emerging devices, for instance, memristors, provide a promising path to address these issues. Although innovative memristor devices and circuit designs have been proposed for neuromorphic computing and applied to different proof-of-concept applications, there is still a long way to go to build large-scale low-power memristor-based neuromorphic systems that can bridge the gap between AI and biological brains. This Perspective summarizes the progress and challenges from memristor devices to neuromorphic systems and proposes possible directions for neuromorphic system implementation based on memristive devices.

Evolving Tangent Hyperbolic memristor based 6D chaotic model with fractional order derivative: Analysis and applications

The nonlinear dynamics of fractional order systems and memristor based circuits have attracted an escalating attention in recent years. This paper reports on a novel six dimensional nonlinear dynamical system with a tangent hyperbolic memristor circuit and amalgamated image encryption. The dynamical system is analyzed using standard tools, including phase portraits, equilibrium points, Eigenvalues, Routh–Hurwitz stability criterion, Lyapunov exponents and bifurcation diagrams. The analysis suggests that the developed system is chaotic in nature and has exciting new 2D and 3D trajectories that have not been reported before. The chaotic system is numerically solved for different values of the fractional order q, and the results of equilibrium points and Lyapunov exponents are mentioned in tables. Fractional order circuits are designed for q=1 and q=0.99 utilizing the approximation fractional order technique of the transfer function. The developed circuit is generalized in a way that the circuit can work for both the integer and non-integer fractional order values by just introducing the fractional block to make it work for q=0.99, and removing it with a conventional integrator capacitor to work for q=1. The circuit simulation and numerical results were compared, and signifying that they were both in good agreement with each other. Lastly, the random number generated from the chaotic system is utilized to scramble the image via the scheme of Amalgamated Image Encryption. The scrambled image was tested using different image security test algorithms to support the idea that the chaotic system and image can together form an advantageous key.

A Memristive Synapse Control Method to Generate Diversified Multistructure Chaotic Attractors

Due to the synapse-like nonlinearity and memory characteristics, memristor is often used to construct memristive neural networks with complex dynamical behaviors. However, memristive neural networks with multistructure chaotic attractors have not been found yet. In this article, a novel method for designing multistructure chaotic attractors in memristive neural networks is proposed. By utilizing a multipiecewise memristive synapse control in a Hopfield neural network (HNN), various complex multistructure chaotic attractors can be produced. Theoretical analysis and numerical simulation demonstrate that multiple multistructure chaotic attractors with different topologies can be generated by conducting the memristive synapse-control in different synaptic coupling positions. Differing from traditional multiscroll attractors, the generated multistructure attractors contain multiple irregular shapes instead of simple scrolls. Meanwhile, the number of structures can be easily controlled with the memristor control parameters. Furthermore, we design a module-based analog memristive neural network circuit and the arbitrary number of multistructure attractors can be obtained by selecting corresponding control voltages. Finally, based on the memristive HNNs, a novel image encryption cryptosystem with a permutation-diffusion structure is designed and evaluated, exhibiting its excellent encryption performances, especially the extremely high key sensitivity.

Temperature Control of Diffusive Memristor Hysteresis and Artificial Neuron Spiking

Memristive devices are promising elements for energy-efficient neuromorphic computing and future artificial-intelligence systems. For diffusive memristors, resistive switching occurs because of the sequential formation and rupture of conduction filaments between device electrodes due to drift and diffusion of silver nanoparticles in the dielectric matrix. This process is governed by the applied electric voltage. Here, both in experiment and in simulations we demonstrate that varying temperature offers an efficient control of memristor states and charges transport in the device. By raising and lowering the device temperature it is shown that the memristive state can be reset, even if it cannot be done by varying the applied voltage. In addition, a change in the spiking regime is observed when the spiking is generated in the memristive circuit at a constant applied voltage, but different device temperatures. Our simulations demonstrate a good qualitative agreement with the experiments, and help to explain the effects reported.

Amorphous ITZO-Based Selector Device for Memristor Crossbar Array

In the era of digital transformation, a memristor and memristive circuit can provide an advanced computer architecture that efficiently processes a vast quantity of data. With the unique characteristic of memristor, a memristive crossbar array has been utilized for realization of nonvolatile memory, logic-in-memory circuit, and neuromorphic system. However, the crossbar array architecture suffers from leakage of current, known as the sneak current, which causes a cross-talk interference problem between adjacent memristor devices, leading to an unavoidable operational error and high power consumption. Here, we present an amorphous In-Sn-Zn-O (a-ITZO) oxide semiconductor-based selector device to address the sneak current issue. The a-ITZO-selector device is realized with the back-to-back Schottky diode with nonlinear current-voltage (I-V) characteristics. Its nonlinearity is dependent on the oxygen plasma treatment process which can suppress the surface electron accumulation layer arising on the a-ITZO surface. The a-ITZO-selector device shows reliable characteristics against electrical stress and high temperature. In addition, the selector device allows for a stable read margin over 1 Mbit of memristor crossbar array. The findings may offer a feasible solution for the development of a high-density memristor crossbar array.

Neuromorphic behaviors of a symmetric LAM-based electronic neuron circuit: Numerical simulation and experimental measurement

Memristor-based neuromorphic computing can achieve the scalability and biological fidelity simultaneously by flexible applying the neuromorphic behaviors. The locally-active memristor (LAM) can work on the edge of chaos associating to stable yet excitable subdomain, which is regarded as a natural candidate in generating neuromorphic behaviors. This paper proposes a new LAM possessing origin symmetric DC characteristic and locally-active domains (LADs) is investigated in-depth and the edge of chaos in its LADs is explored. Afterwards, a second-order memristive circuit is built. Then, the Jacobi matrix-based stability and admittance function are theoretically and numerically analyzed, from which Hopf bifurcation is disclosed. The oscillating behaviors are revealed at neighborhood of the Hopf bifurcation. Then, a third-order electronic neuron circuit is built by parallel connecting a capacitor to the LAM, and a bipolar square-wave is applied to disclose the neuromorphic behaviors. Numerical results demonstrate that the electronic neuron circuit can generate neuromorphic behaviors of periodic/chaotic spiking. These spiking behaviors can be regulated by the period and duty ratio of the applied bipolar square-wave. Finally, FPGA-based experimental measurements validate the numerical simulations. What’s more, these numerical simulations and experimental measurements effectively show the feasibility of the LAM in constructing memristive circuit to generate neuromorphic behaviors.

Self-Assembled TaOX/2H-TaS2 as a van der Waals Platform of a Multilevel Memristor Circuit Integrated with a β-Ga2O3 Transistor.

Two-dimensional (2D)-layered material tantalum disulfide (2H-TaS2) is known to be a van der Waals conductor at room temperature. Here, 2D-layered TaS2 has been partially oxidized by utraviolet-ozone (UV-O3) annealing to form a 12-nm-thin TaOX on conducting TaS2, so that the TaOX/2H-TaS2 structure might be self-assembled. Utilizing the TaOX/2H-TaS2 structure as a platform, each device of a β-Ga2O3 channel MOSFET and a TaOX memristor has been successfully fabricated. An insulator structure of Pt/TaOX/2H-TaS2 shows good a dielectric constant (k ∼ 21) and strength (∼3 MV/cm) of achieved TaOX, which is enough to support a β-Ga2O3 transistor channel. Based on the quality of TaOX and low trap density of the TaOX/β-Ga2O3 interface, which is achieved via another UV-O3 annealing, excellent device properties such as little hysteresis (<∼0.04 V), band-like transport, and a steep subthreshold swing of ∼85 mV/dec are achieved. With a Cu electrode on top of the TaOX/2H-TaS2 structure, the TaOX acts as a memristor operating around ∼2 V for nonvolatile bipolar and unipolar mode memories. The functionalities of the TaOX/2H-TaS2 platform become more distinguished finally when the Cu/TaOX/2H-TaS2 memristor and β-Ga2O3 MOSFET are integrated to form a resistive memory switching circuit. The circuit nicely demonstrates the multilevel memory functions.

Biphasic action potential and chaos in a symmetrical Chua Corsage Memristor-based circuit.

Neuromorphic computing provides unique computing and memory capabilities that could break the limitation of conventional von Neumann computing. Toward realizing neuromorphic computing, fabrication and synthetization of hardware elements and circuits to emulate biological neurons are crucial. Despite the striking progress in exploring neuron circuits, the existing circuits can only reproduce monophasic action potentials, and no studies report on circuits that could emulate biphasic action potentials, limiting the development of neuromorphic devices. Here, we present a simple third-order memristive circuit built with a classical symmetrical Chua Corsage Memristor (SCCM) to accurately emulate biological neurons and show that the circuit can reproduce monophasic action potentials, biphasic action potentials, and chaos. Applying the edge of chaos criterion, we calculate that the SCCM and the proposed circuit have the symmetrical edge of chaos domains with respect to the origin, which plays an important role in generating biphasic action potentials. Also, we draw a parameter classification map of the proposed circuit, showing the edge of chaos domain (EOCD), the locally active domain, and the locally passive domain. Near the calculated EOCD, the third-order circuit generates monophasic action potentials, biphasic action potentials, chaos, and ten types of symmetrical bi-directional neuromorphic phenomena by only tuning the input voltage, showing a resemblance to biological neurons. Finally, a physical SCCM circuit and some experimentally measured neuromorphic waveforms are exhibited. The experimental results agree with the numerical simulations, verifying that the proposed circuit is suitable as artificial neurons.

A Kind of Optoelectronic Memristor Model and Its Applications in Multi-Valued Logic

Memristors have been proved effective in intelligent computing systems owing to the advantages of non-volatility, nanometer size, low power consumption, compatibility with traditional CMOS technology, and rapid resistance transformation. In recent years, considerable work has been devoted to the question of how to design and optimize memristor models with different structures and physical mechanisms. Despite the fact that the optoelectronic effect inevitably makes the modelling process more complex and challenging, relatively few research works are dedicated to optoelectronic memristor modelling. Based on this, this paper develops an optoelectronic memristor model (containing mathematical model and circuit model). Moreover, the composite memristor circuit (series- and parallel-connected configuration) with a rotation mechanism is discussed. Further, a multi-valued logic circuit is designed, which is capable of performing multiple logic functions from 0–1, verifying the validity and effectiveness of the established memristor model, as well as opening up a new path for the circuit implementation of fuzzy logic.

A low-power reconfigurable memristor for artificial neurons and synapses

With the advancement of artificial intelligence technology, memristors have aroused the interest of researchers because they can realize a variety of biological functions, good scalability, and high running speed. In this work, the amorphous semiconductor material silicon carbide (SiC) was used as the dielectric to fabricate the memristor with the Ag/SiC/n-Si structure. The device has a power consumption as low as 3.4 pJ, a switching ratio of up to 105, and a lower set voltage of 1.26 V, indicating excellent performance. Importantly, by adjusting the current compliance, the strength of the formed filaments changes, and the threshold characteristic and bipolar resistance switching phenomenon could be simultaneously realized in one device. On this basis, the biological long- and short-term memory process was simulated. Importantly, we have implemented leakage integration and fire models constructed based on structured Ag/SiC/n-Si memristor circuits. This low-power reconfigurable device opens up the possibilities for memristor-based applications combining artificial neurons and synapses.

Implementation of the Simple Hyperchaotic Memristor Circuit with Attractor Evolution and Large-Scale Parameter Permission

A novel, simple, four-dimensional hyperchaotic memristor circuit consisting of two capacitors, an inductor and a magnetically controlled memristor is designed. Three parameters (a, b, c) are especially set as the research objects of the model through numerical simulation. It is found that the circuit not only exhibits a rich attractor evolution phenomenon, but also has large-scale parameter permission. At the same time, the spectral entropy complexity of the circuit is analyzed, and it is confirmed that the circuit contains a significant amount of dynamical behavior. By setting the internal parameters of the circuit to remain constant, a number of coexisting attractors are found under symmetric initial conditions. Then, the results of the attractor basin further confirm the coexisting attractor behavior and multiple stability. Finally, the simple memristor chaotic circuit is designed by the time-domain method with FPGA technology and the experimental results have the same phase trajectory as the numerical calculation results. Hyperchaos and broad parameter selection mean that the simple memristor model has more complex dynamic behavior, which can be widely used in the future, in areas such as secure communication, intelligent control and memory storage.

Memristive chaotic circuits and systems

Memristive chaotic circuits and systems

Design and Implementation of a Flexible Neuromorphic Computing System for Affective Communication via Memristive Circuits

Neuromorphic computing is expected to realize fast and energy-efficient artificial neural networks and address the inherent limitations of von Neumann architectures in dedicated communication applications. To realize this vision, we identify the existing challenges in neuromorphic computing and provide a specific solution from the perspectives of device, circuit, and system. At the device level, we fabricate a metal-oxide-based memristor with high stability, low power, and good scalability, serving as the fundamental component of a neuromorphic computing system. At the circuit level, the basic circuit units and necessary peripheral circuits are designed to realize efficient vector-matrix multiplication and different functions, including nonlinear activation operation, subtraction operation, added operation, and so on. At the system level, a flexible neuromorphic computing system with a hardware-friendly training approach is proposed, which can perform effective communication with good trade-off between accuracy and time consumption. This study is expected to achieve the deep integration of nanotechnology, energy-efficient integrated circuits, and neuromorphic computing systems into communication applications.