Memory Thin-film Transistors Research Articles

Non-Volatile Memory Based on ZnO Thin-Film Transistor with Self-Assembled Au Nanocrystals.

Non-volatile memory based on thin-film transistor is crucial for system-on-panel and flexible electronic systems. Achieving high-performance and reliable thin-film transistor (TFT) memory still remains challenging. Here, for the first time, we present a ZnO TFT memory utilizing self-assembled Au nanocrystals with a low thermal budget, exhibiting excellent memory performance, including a program/erase window of 9.8 V, 29% charge loss extrapolated to 10 years, and remarkable endurance characteristics. Moreover, the memory exhibits favorable on-state characteristics with mobility, subthreshold swing, and current on-off ratio of 17.6 cm2V-1s-1, 0.71 V/dec, and 107, respectively. Our study shows that the fabricated TFT memory has great potential for practical applications.

Non-Volatile Memory Thin-Film Transistors Using Oxide Semiconductor as Both Active and Charge Trapping Layer

Non-Volatile Memory Thin-Film Transistors Using Oxide Semiconductor as Both Active and Charge Trapping Layer

Ultrahigh-Speed In-Memory Electronics Enabled by Proximity-Oxidation-Evolved Metal Oxide Redox Transistors.

The pursuit of a universal device that combines nonvolatile multilevel storage, ultrafast writing/erasing speed, nondestructive readout, and embedded processing with low power consumption demands the development of innovative architectures. Although thin-film transistors and redox-based resistive-switching devices have independently been proven to be ideal building blocks for data processing and storage, it is still difficult to achieve both well-controlled multilevel memory and high-precision ultrafast processing in a single unit, even though this is essential for the large-scale hardware implementation of in-memory computing. In this work, an ultrafast (≈42ns) and programable redox thin-film transistor (ReTFT) memory made of a proximity-oxidation-grown TiO2 layer is developed, which has on/off ratio of 105 , nonvolatile multilevel analog storage with a long retention time, strong durability, and high reliability. Utilizing the proof-of-concept ReTFTs, circuits capable of performing fundamental NOT, AND, and OR operations with reconfigurable logic-in-memory processing are developed. Further, on-demand signal memory-processing operations, like multi-terminal addressable memory, learning, pattern recognition, and classification, are explored for prospective application in neuromorphic hardware. This device, which operates on a fundamentally different mechanism, presents an alternate solution to the problems associated with the creation of high-performing in-memory processing technology.

Synergic Impacts of CF4 Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO2 Charge Trap and In–Ga–Zn–O Active Channel Layers

Synergic Impacts of CF₄ Plasma Treatment and Post-thermal Annealing on the Nonvolatile Memory Performance of Charge-Trap-Assisted Memory Thin-Film Transistors Using Al–HfO₂ Charge Trap and In–Ga–Zn–O Active Channel Layers

Characterization of nanoscale vertical-channel charge-trap memory thin film transistors using oxide semiconducting active and trap layers

We fabricated vertical-channel charge-trap memory thin film transistors (V-CTM TFTs) using an In–Ga–Zn–O channel and ZnO charge trap layers, in which a solution-processed SiO2 spacer pattern was introduced to scale down the vertical-channel length below 190 nm. The vertical gate-stack structure was implemented by atomic-layer deposition with excellent film conformality. The V-CTM TFTs with channel lengths of 190 (S1) and 140 nm (S2) showed charge-trap-assisted wide memory windows of 12.0 and 10.1 V, respectively. The memory margins between the on- and off-programmed currents were estimated to be 1.2 × 105 and 5.1 × 102 with a program pulse duration of 100 ms for S1 and S2, respectively. The programmed states did not exhibit any degradation with a lapse of retention for 104 s. With reducing the channel length, the number of endurance cycles decreased from 5000 to 3000 cycles. A vertical integration of oxide-based CTM device scaled down to sub-150 nm could be verified to show sound nonvolatile memory operations, even though there remain some technical issues such as a higher level of off-current for S2.

Flexible and Printed Organic Nonvolatile Memory Transistor with Bilayer Polymer Dielectrics

AbstractIn this study, printed organic nonvolatile memory thin‐film transistors (TFTs) with phase‐separated tunneling layer is presented. Finely patterned electrodes are fabricated by reverse‐offset printing with 15 μm line width and 10 μm channel length. Memory devices are configured in a bottom‐gate bottom‐contact TFT structure with a high‐k gate blocking insulator poly(vinylidene fluoride‐co‐trifluoroethylene). A blended ink, which consisted of a small‐molecule p‐type organic semiconductor dithieno[2,3‐d;2′,3′‐d′]benzo[1,2‐b;4,5‐b′]dithiophene and a polystyrene dielectric, is fabricated using air‐pulse nozzle printing. The tunneling layer is formed during the active layer printing process with the blended ink by phase separation of small‐molecule and polymer. The printed memory TFTs with the phase‐separated tunneling layer exhibit significantly improved VTH shifts (≈3 times), programmed/erased current ratio (>103 A A−1), switching speed (<100 ms), and estimated data retention (>10 years). This memory device can be applied to wearable electronics, smart Internet‐of‐Things devices, and neuromorphic computing devices.

Characteristics of a Multiple-Layered Graphene Oxide Memory Thin Film Transistor with Gold Nanoparticle Embedded as Charging Elements

In this study, we report the highest mobility in the reduced graphene oxide- (rGO-) based TFTs embedded with Au NPs. In addition, we fabricated a reduced graphene oxide memory device (rGO-capacitor), a reduced graphene oxide thin film transistor (rGO-TFT), and a reduced graphene oxide memory thin film transistor (rGO-MTFT) and characterized their electrical performances. While the rGO-TFT device was investigated for nonambipolar channel performance, the rGO-capacitor and rGO-MTFT were examined for nonvolatile memory capabilities in a metal-graphene-insulator-silicon (MGIS) structure. The incorporation of the gold nanoparticles (Au NPs) between the rGO and an insulator silicon dioxide (SiO2) layer served as a charging element. The rGO-capacitor revealed the memory effect of hysteretic capacitance-voltage (C-V) loops, and the flat-band voltage shift ( Δ V FB ) was measured as 0.1375 V after 100 s retention time. The rGO-TFT shows the p-channel characteristics with high hole mobility of 16.479 cm2/V⋅s. The threshold voltage shift ( Δ V th ) of the rGO-MTFT was detected as 5.74 V from 10 V to -30 V sweep, demonstrating high mobility of 22.887 cm2/V⋅s.

An organic field effect transistor memory adopting octadecyltrichlorosilane self-assembled monolayer

An organic nonvolatile memory is proposed based on octadecyltrichlorosilane self-assembled monolayer (ODTS SAM) and copper hexadecafluorophthalocyanine (F16CuPc) heterostructure, where F16CuPc acts as the active layer of the organic thin film transistor memory device, and ODTS SAM functions as the charge trapping layer. By adopting N-type active layer, sufficient electrons ensure the erasing process that is independent of the light illumination, indicating a fully electrically driving memory device, where large memory window is obtained. AFM images demonstrates that the monolayer provides the trapping sites. The trapping mechanism is analyzed based on the electric dipoles theory, the dipoles orientation in the monolayer is critical for providing trapping sites, which fixes the mobile carriers at the ODTS SAM/F16CuPc interface. The writing–reading–erasing–reading (WRER) tests and the retention time are shown, and they can be further optimized by involving a thin polystyrene tunneling layer between active layer and charge trapping layer, with an retention time of approximately 125 d, and a sufficient WRER reading current ratio of more than 103 for practical fully electrically driving binary nonvolatile memory device applications.

Performance enhancement and mechanism exploration of all-carbon-nanotube memory with hydroxylation and dehydration through supercritical carbon dioxide

Carbon nanotubes based non-volatile memories (NVMs) with excellent electronic properties can provide high bit density and energy efficiency. But with the limit of the process conditions, obtaining steep flanks with large hysteresis is still a challenge, while it is the prerequisite for stable program/erase/read operations. Herein, we adopt a novel treatment of supercritical CO2 (SCCO2) fluids to improve the performance of all-carbon-nanotube thin-film transistor (A-CNT-TFT) memory elements. By the treatment, the transfer characteristics of the A-CNT-TFTs achieve a 13.20 V hysteresis window, which is larger than 50% of the whole sweeping-voltage range. The disappearance of hump effect greatly improves the switching characteristics. The material analysis confirms that the SCCO2 fluids can reduce the defects in dielectric layer sufficiently and strengthen the connection between channel and gate dielectric. Furthermore, it is proposed that existence of hydroxyl groups in the carbon nanotubes contributes dominantly to the mechanism for charge storage, and the SCCO2 treatment enhances the charge storage by increasing the number of the hydroxyl groups. The work shows that the low-temperature SCCO2 treatment can better improve the performance of A-CNT-TFTs, which provides a promising option for nonvolatile charge storage memory devices.

Improvement in Mechanical Durability of Stretchable Charge-Trap Memory Transistors with Engineered Wavy-Dimensional Structures

Charge-trap memory thin-film transistors (CTM-TFTs) were fabricated with wavy-dimensional structures, and their device performances were demonstrated under mechanically stretching conditions. The f...

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.0 V at a VGS sweep of ±20 V and a large memory margin of 1.6 × 102 at a program pulse duration as short as 5 ms. The programmed memory margin higher than 105 did not experience any degradation with time evolution for 104 s. The mechanical durability was also evaluated after the delamination process of polyimide (PI) film. There were no marked variations in charge-trap-assisted MW even at a curvature radius of 1 mm and programmed memory margin even after repeated program operations of 104 cycles. The introduction of ALD process for the formation of IGZO active channel was suggested as a main process parameter to ensure the excellent memory device characteristics of the V-CTM TFTs.

Phase‐Separated, Printed Organic Thin‐Film Transistor‐Based Nonvolatile Memory with Enhanced Data Retention

AbstractA nonvolatile memory thin film transistor (TFT) is an essential building block in all electronic applications for calculation and identification. In particular, organic memory TFTs using bilayered polymer electrets have attracted significant attention due to excellent mechanical flexibility and fast operating speed. However, the data retention characteristics over an extended period of time remains a major reliability issue for nonvolatile memory devices. Here, the enhancement of data retention in flexible and printed organic memory TFTs by introducing a phase‐separated tunneling layer is demonstrated. The tunneling layer is formed during an active layer printing process with a blend ink of small‐molecule organic semiconductor and polystyrene insulator. The effect of the dielectric tunneling layer on data retention characteristics is systematically investigated. The printed nonvolatile memory devices with the phase‐separated tunneling layer exhibit significantly improved data retention time of over 10 years, validating the feasibility of applying flexible memory into wearable electronics and smart Internet‐of‐Things devices.

Nanoparticle floating-gate transistor memory based on solution-processed ambipolar organic semiconductor

Organic thin-film transistor memory based on nano-floating-gate nonvolatile memory was demonstrated by a simple method. The gold nanoparticle that fabricated by thermally evaporated acted as the floating gate. Spin coated PMMA film acted as the tunneling layer. A solution-processed ambipolar semiconductor acted as the active layer. Because of the existence of both hole and electron carriers in bipolar semiconductor materials, it is more conducive to the editing and erasing of memories under positive and negative pressure. The memory based on metal nanoparticles and organic bipolar semiconductor shows good read-write function.

Characterization on the operation stability of mechanically flexible memory thin-film transistors using engineered ZnO charge-trap layers

The charge-trap memory thin-film transistors (CTM-TFTs) using ZnO charge-trap layer (CTL) were fabricated and characterized, in which ZnO CTL was deposited by atomic layer deposition (ALD) and the deposition temperatures were controlled to be 75, 100, and 125 °C to improve both specifications of device characteristics and stability for the flexible memory devices. The CTM-TFT using ZnO CTL deposited at 100 °C obtained a wide memory window (MW) of 14.7 V, large memory margin between ON- and OFF-states (ION/IOFF, 7.3 × 106) at 1 µs voltage pulses. The ION/IOFF larger than 107 was also obtained with a progress of retention time. It was noteworthy that the deposition temperature for the ZnO CTL was worked as one of the most important control parameters affecting the memory device characteristics of the fabricated flexible CTM-TFTs. Alternatively, the fast program operation and long retention time were suggested to result from a suitable number of trap sites and their appropriate positions within the ZnO CTL prepared at 100 °C. The improved device stabilities were guaranteed even under bending condition at a radius of curvature of 10 mm after the delamination process of PI film substrate from carrier glass.

Charge-trap-assisted flexible nonvolatile memory applications using oxide-semiconductor thin-film transistors

We introduce mechanically flexible nonvolatile memory thin-film transistors (MTFTs) for future highly functional flexible and stretchable electronic devices and systems. The proposed memory devices are uniquely composed of oxide-semiconductor thin films and operated with charge-trap and detrap mechanisms for nonvolatile memory operations. Charge-trap-assisted MTFTs (CT-MTFTs) using In–Ga–Zn–O active and ZnO charge-trap layers are designed and fabricated on flexible poly(ethylene naphthalate) and colorless polyimide films prepared on carrier glass substrates. We describe the fabrication processes and evaluation methodologies for realizing flexible CT-MTFTs in a detailed way and discuss related technical issues. The device characteristics and memory performance of the fabricated flexible CT-MTFTs, including when the devices are mechanically strained, are extensively discussed. We also propose further improvements for remaining issues on device performance from the viewpoints of memory operations and mechanical flexibility.

Impacts of Bottom-gate Bias Control for Low-voltage Memory Operations of Charge-trap Memory Thin Film Transistors using Oxide Semiconductors

We fabricated and characterized the double-gate (DG) charge-trap memory thin film transistors (CTM-TFTs) using In-Ga-Zn-O active and ZnO charge-trap layers. The fabricated device exhibited a charge-trap-assisted memory window as wide as 13.8 V using a DG mode operation and a program/erase (P/E) speed faster than 10 μs. These memory device characteristics were examined by controlling the fixed bias voltage applied at the bottom gate (VSUBBG/SUB) and the capacitance coupling ratio between top and bottom gate insulators, which could be strategically designed with the DG configuration. The capacitance coupling ratio was varied by changing the bottom gate insulator (BGI) thickness between 50 and 100 nm. For the CTM-TFT with a BGI thickness of 100 nm, 3.1×10SUP6/SUP was obtained for the memory on/off ratio with P/E voltages of ± 15 V and a fixed VSUBBG/SUB of -3 V. Overall, our results suggest that the DG configuration can remarkably enhance the P/E speed and memory on/off ratio by suitably controlling the fixed VSUBBG/SUB conditions and the capacitance coupling ratio in CTM-TFTs.

Impacts of HfO2/ZnO Stack-Structured Charge-Trap Layers Controlled by Atomic Layer Deposition on Nonvolatile Memory Characteristics of In-Ga-Zn-O Channel Charge-Trap Memory Thin-Film Transistors

We fabricated the charge-trap memory thin film transistors (CTM-TFTs) using InGaZnO (IGZO) active channel and HfO2/ZnO stack-structured charge-trap layer (CTL). To investigate the effects of the number and thickness of HfO2 layers inserted between the ZnO within the stack structured CTLs on the device characteristics, 2-nm-thick HfO2 thin films were inlaid once, twice, and four times, and 4-nm-thick HfO2 layers were introduced twice between the ZnO layers. The CTM-TFTs using the stack structured CTLs with 4-nm-thick HfO2 layers showed good memory characteristics, including large memory window (MW) of 25 V and rapid program/erase (P/E) speed of 500 $\mu \text{s}$ because of high total trap density of HfO2 with a sufficient thickness to provide charge-trap centers. On the contrary, relatively narrow MW of 16 V and slower P/E speed of 100 ms were obtained for memory device using the stacked CTL with four HfO2 layers of 2 nm. The HfO2 layer with a thickness as thin as 2 nm was supposed to act as just dielectric films deactivating the trapping or migration of electron charges due to too thin film thickness. The gate-stack structures confirmed from STEM images suggested that the modulations in memory device characteristics with different CTL structures resulted from the variations in designs of stack structured CTLs when the interface qualities within the gate-stacks were well prepared. Moreover, the detailed fabrication conditions were found to be important control parameters to reproducibly obtain reliable memory device characteristics.

Introduction of lithography-compatible conducting polymer as flexible electrode for oxide-based charge-trap memory transistors on plastic poly(ethylene naphthalate) substrates

To realize highly-functional flexible nonvolatile memories, the organic/inorganic hybrid structures were introduced as suitable approaches to exploit both advantages of flexibility of organic materials and the electrical performance of inorganic materials. Electrically conductive poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) thin film was transferred on plastic poly(ethylene naphthalate) (PEN) substrates and then patterned by conventional photo-lithography process through the optimization of the surface properties in terms of the enhanced interaction between the PEDOT:PSS and the PEN substrate. The gate-stack structure of the charge-trap memory thin-film transistors was designed to be Al2O3 blocking/ZnO charge-trap/Al2O3 tunneling/In-Ga-Zn-O active/PEDOT:PSS source-drain layers. The fabricated device showed the nonvolatile memory operations including charge-trap-assisted memory window. However, the long-tapered rough patterns of PEDOT:PSS and damaged back-channel on organic barrier were demonstrated to be feasible origins for some drawbacks including the high contact resistance of the fabricated prototype device. Appropriate ideas for further improvements memory device characteristics was also suggested.

Solution-processed nonvolatile Hf-doped ZnO thin-film transistor memory with SiO2 micro- and nanoparticles as a trapping medium

We report a nonvolatile-memory device based on solution-processed Hf-doped ZnO (ZnO:Hf) thin-film transistors (TFTs) fabricated by inserting SiO2 microparticles (MPs) and nanoparticles (NPs) as a charge trapping medium. The transfer characteristics of ZnO:Hf TFT devices inserted with SiO2 particles showed a large clockwise hysteresis behavior owing to charge carrier trapping capability. Both memory devices exhibited a highly programmable memory window during the program/erase operation, which can be attributed to charge carrier trapping and de-trapping in SiO2 particles. Particularly, the memory device with SiO2 NPs revealed a larger memory window over 25 V than that with MPs. Furthermore, the fabricated memory devices showed remarkably long-term retention characteristics and the ON/OFF current ratio greater than 104.

42‐1: A Promising Strategy of Low‐Power Circuit Design for Integrated Display Driver Using Charge‐Trap Memory and Oxide Thin Film Transistors

We propose the design concept for dramatically reducing the power consumption of integrated circuit using TFTs, which is named as Read‐out Modulation (RoM). In the RoM scheme, the read‐out voltages applied to the charge‐trap memory TFTs are intentionally modulated to replace the clocks of shift registers to minimize the clocking power consumption. The test circuit is fabricated and the proposed RoM is successfully verified with the frequency characteristics.