Memory Interface Research Articles

Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.

Variability-insensitive scheme for NAND flash memory interfaces

A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

60.2: Dynamic Bit-Rate Allocation of High-Compression Feedforward Driving

We have developed High Compression Feedforward Driving (hcFFD) that can compress the image data stored in the frame memory of overdrive down to 1/6. Together with the optimization of the encoding parameters of macFFD, which belongs to the previous generation, this hcFFD technique corrects the response time of liquid crystal with smaller and less memory by means of a system that dynamically controls the bit rate allocated to the luminance signal and the color signal. This 1/6 reduction of image data allows us to structure a memory interface with a 16-bit data bus even on high-definition LCD panels, ensuring both low cost and secured performance.

Heterogeneous embedded system with “microcontroller‐CPLD” based shared memory interface for sensor applications

PurposeAims to design a heterogeneous embedded system with CPLD and microcontroller as co‐processors sharing a memory module.Design/methodology/approachThe system receives external analog input signal, which is applied to the PIC 16F73 microcontroller. Upon converting the data in to digital format using the on‐chip ADC, the PIC stores the digitized version in the SRAM (HCM 6264) chip. SRAM HCM 6264 has been used as a shared memory model, of which both the PIC and CPLD can access all the locations. Once the PIC passes controls to the CPLD, the further processing is carried out by the CPLD without any intervention of the PIC. This is a true example of co‐processing of the architecturally diversified computing modules from completely different vendors with totally different programming suits.FindingsThe board has been tested with IC temperature sensors and also found to be useful for sensor array applications involving three types of processing viz. analog (through instrumentation amplifier), real‐time digital (through microcontroller) and customized reconfigurable digital (with the CPLD).Practical implicationsThe system has several potential applications in avionics, military and robotic embedded systems, which have inherent real‐time constraints that need to be supported by the underlying hardware and driver programs.Originality/valueDiscusses the rare and unique combination of diversified processing core to build an embedded system.

A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor

In this presentation, we will deal with verification of custom designed embedded memories. Using our paradigm, one can abstract the behavior of a memory block by a couple of artifacts--one representing its contents, and another representing its interface. We make use of the well known behavioral model known as the Efficient Memory Model (EMM) [29, 30] to represent contents of memories. We provide a methodology using which the behavior of a switch (or equivalently, transistor) level device can be specified using parameterized regular expressions. These entities can be used to abstractly describe the behavior of a bunch of switches that represent the interface of a memory. An automaton that we construct out of an abstract memory interface definition represents an abstraction of the memory interface itself. We show that such an automaton also forms a transducer that is a simulation model in a symbolic simulation environment. An EMM representing a memory core in conjunction with a transducer representing its interface is used as an abstraction of a complete memory during our automatic verification process.We also present a language formalism using which we show that the outputs from the transducers that are generated from the abstract specifications are weaker than or equal to the outputs defined by the regular expressions, in a partially ordered output space. We show that although the regular expressions are defined over exact and legal input strings, the transducers computed from them can provide outputs even when provided with weak or illegal input strings. This is an absolute necessity in order to have the capability to produce outputs when treated as a reactive system embedded in a symbolic simulation environment. Thus, we show that the simulation model generated by our technique is an conservative approximation of the corresponding abstract specification.We present a simple theory of composition that can be used to compose different simulation models used in our technique. Memories consisting of several ports result into several user-provided abstract specifications, which in turn result into several transducers that can be composed into a single transducer. That transducer in turn can be composed to a simulation model of an EMM. Our simple theory of composition also enables one to compose the abstract state space a memory core along with its ports with the concrete state space of the circuitry surrounding the memory core. We have shown that the composite simulation model representing the complete circuit has a partially ordered state space that (a) forms a complete lattice, and (b) that has a monotonic state transition function, that makes it suitable for being used in a symbolic simulation environment making use of Symbolic Trajectory Evaluation (STE) [27].The verification paradigm used is STE. For Motorola high performance microprocessors, switch level models are hand designed assuming that corresponding RTLs are golden models. Therefore, checking of equivalence between the two models is of absolute necessity as the RTL needs to be predictive of silicon behavior. We have developed a tool based on the proposed technique and used it to check that RTL descriptions of custom memories have been correctly implemented by transistor level descriptions of the same, augmented with abstract specifications of their cores. Our example circuits were taken from the state of the art Motorola MPC7450 microprocessor, a Motorola PowerPC. Experimental evidence testify to the effectiveness of the technique in catching subtle bugs in data path circuitry.

An efficient quality-aware memory controller for multimedia platform SoC

The ongoing advancements in VLSI technology allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory controller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory interface socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Experimental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%-65% and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.

A Compiler for Mapping a Rule-Based Event-Triggered Program to a Hardware Engine

In this paper we describe the RERAL compiler. RERAL is a Rule-based Event-driven Routing Algorithm Language. It is intended for the configuration of a router for regular networks, as found in parallel computers or computer clusters. The language combines predicate-logic-derived functional expressions with Petri-net-based asynchronity. The high performance requirements (a routing decision should take no more than few nanoseconds) imply sophisticated optimization methods in the compiler, in particular, flattening the program hierarchy, unrolling loops and mapping high-level program fragments to available application-specific hardware units.We also point out a new application area of the concept, namely the management of a memory interface in a system-on-chip for increased bandwidth utilization.

Low-power RT-level synthesis techniques: a tutorial

Power consumption and power-related issues have become a first-order concern for most designs and loom as fundamental barriers for many others. While the primary method used to date for reducing power has been supply voltage reduction, this technique begins to lose its effectiveness as voltages drop to below one volt and further reductions in the supply voltage begin to create more problems than are solved. Under these circumstances, the process of design and the automation tools required to support that process become the critical success factors. In the last decade, huge effort has been invested to come up with a wide range of design solutions that help solve the power dissipation problem for different types of electronic devices, components and systems. These techniques range from RTL power management and multiple voltage assignment, to power-aware logic synthesis and physical design, to memory and bus interface design. A number of representative low-power design techniques from this large set are explained. More precisely, basic techniques are described, that are applicable at RT-level and below, and have proved to hold good potential for power optimisation in practical design environments.

Performance and area modeling of complete FPGA designs in the presence of loop transformations

Selecting which program transformations to apply when mapping computations to FPGA-based computing architectures can lead to prohibitively long design space exploration cycles. An alternative is to develop fast, yet accurate, performance and area models to quickly understand the Impact and interaction of the transformations. In this paper, we present a combined analytical performance and area modeling approach for complete FPGA designs in the presence of loop transformations. Our approach takes into account the impact of input/output memory bandwidth and memory interface resources, often the limiting factor in the effective implementation of computations. Our preliminary results reveal that our modeling is very accurate, being therefore amenable to be used in a compiler tool to quickly explore very large design spaces.

On model checking data-independent systems with arrays without reset

A system is data-independent with respect to a data type $X$ iff the operations it can perform on values of type $X$ are restricted to just equality testing. The system may also store, input and output values of type $X$. We study model checking of systems which are data-independent with respect to two distinct type variables $X$ and $Y$, and may in addition use arrays with indices from $X$ and values from $Y$. Our main interest is the following parameterised model-checking problem: whether a given program satisfies a given temporal-logic formula for all non-empty finite instances of $X$ and $Y$. Initially, we consider instead the abstraction where $X$ and $Y$ are infinite and where partial functions with finite domains are used to model arrays. Using a translation to data-independent systems without arrays, we show that the $\mu$-calculus model-checking problem is decidable for these systems. From this result, we can deduce properties of all systems with finite instances of $X$ and $Y$. We show that there is a procedure for the above parameterised model-checking problem of the universal fragment of the $\mu$-calculus, such that it always terminates but may give false negatives. We also deduce that the parameterised model-checking problem of the universal disjunction-free fragment of the $\mu$-calculus is decidable. Practical motivations for model checking data-independent systems with arrays include verification of memory and cache systems, where $X$ is the type of memory addresses, and $Y$ the type of storable values. As an example we verify a fault-tolerant memory interface over a set of unreliable memories.

A scalable instruction buffer and align unit for xDSPcore

Increasing mask costs and decreasing feature sizes together with productivity demand have led to the trend of platform design. Software programmable embedded cores are used to provide the necessary flexibility in integrated systems. Facing increasing system complexity, single-issue digital signal processors (DSPs) have been replaced by cores providing the execution of several instructions in parallel. The most common programming model for multi-issue DSP core architectures is Very Long Instruction Word (VLIW) which is based on static scheduling, and enables minimization of the worst case execution time and reduces core complexity. The drawback of traditional VLIW is poor code density, which leads to high program memory requirements and, therefore, requires a large silicon area of the DSP subsystem. To overcome this problem without limiting the core performance, a scalable long instruction word (xLIW) is introduced. A special align unit is used for implementing the xLIW program memory interface. In this paper, the align unit and its main architectural feature, a scalable instruction buffer, is introduced in detail. xLIW is part of a project for a parameterized DSP core.

Memory subsystem technology and design for the z990 eServer

This paper discusses the technology and design of the first double data rate (DDR) memory subsystem for the IBM zSeries® eServer™. The main storage subsystem accommodates the frequency mismatch between the memory controller and industry-standard synchronous dynamic random-access memory (SDRAM), protects data through error-correction code and SDRAM sparing, and increases overall memory subsystem bandwidth. Each memory card consists of the first synchronous memory interface (SMI) application-specific integrated circuit (ASIC) that is optimized specifically for DDR applications, the SMI-enhanced (SMI-E). The SMI-E controller data interface communicates with the high-speed memory controller on the multichip module through special phase alignment and elastic buffering circuitry that determines the optimal sampling point to reliably receive data from the controller. The SMI-E memory data interface is connected to registered DDR dual inline memory modules running up to 250 Mb/s using 256-Mb and 512-Mb SDRAM technology, thereby allowing memory card densities between 4 GB and 32 GB per card. Because of the increased DDR memory interface bit rates, special attention was paid to the design of the SMI-E substrate and base card to minimize noise. The memory, when used in a fully populated system, has four times more storage capacity than the previous z900 generation.

Reconfigurable co-processor for Kanerva's sparse distributed memory

The implementation on hardware of the first layer of Kanerva's sparse distributed memory (SDM) is presented in this work. The hardware consist on a co-processor board for connection on ISA standard bus of an IBM–PCcompatible computer. The board, named reconfigurable co-processor for SDM(RC-SDM), comprises on Xilinx FPGAs, local random access memory and bus interface circuits. Based on in-system reconfiguration capacity of FPGAs, RC-SDM easily allows change of the characteristics of SDM topology implemented. First results show a speed-up of four times of RC-SDM in relation to a software implementation of the algorithm.

Layout attributes and recall

The spatial arrangement of elements such as icons in a computer interface may influence learning the interface. However, the effects of layout organization on users' information processing is relatively little studied so far. The three experiments of this paper examined two attributes of layouts: spatial grouping by proximity and semantic coherence. Learning was assessed by tasks in which 30 participants recalled icon-like items' labels, locations, or both as a series of study-recall trials. The results show that layout organization interacts with task demands. Semantic organization improves recall of labels, and spatial grouping supports recall of locations. When both labels and locations are learned concurrently, the best recall performance is associated with a simultaneously grouped and semantically coherent layout. However, semantic and spatial organization may interact unexpectedly on learning. The findings are discussed from the viewpoint of information chunking in memory processes and interface design.

A new scalable and reconfigurable architecture

As optical link speeds get faster, demands for performance and embedded network services impose increasing flexibility demands. Internet routers must become more efficient and programmable. A new hardware architecture using a dynamic reconfigurable logic (DRL) circuit, along with its design methodology, is proposed. Our approach is to allocate all resources using the dynamic reconfigurable control switch (DRCS). The design space for scheduling the DRL for the networking application (router) is explored. Our proposal outperforms recent network processors since it has a better memory interface and because chained nodes of a thread can be executed at once. Our architecture offers an attractive alternative to expensive commercial solutions employing multiple content addressable memory (CAM) devices and application specific integrated circuits (ASICs). By providing high-performance at low per-ports costs, our architecture is a prime candidate for system-on-chip (SoC) solutions for next generation programmable router port processors.

Scalable IP lookup for internet routers

Internet protocol (IP) address lookup is a central processing function of Internet routers. While a wide range of solutions to this problem have been devised, very few simultaneously achieve high lookup rates, good update performance, high memory efficiency, and low hardware cost. High performance solutions using content addressable memory devices are a popular but high-cost solution, particularly when applied to large databases. We present an efficient hardware implementation of a previously unpublished IP address lookup architecture, invented by Eatherton and Dittia (see M.S. thesis, Washington Univ., St. Louis, MO, 1998). Our experimental implementation uses a single commodity synchronous random access memory chip and less than 10% of the logic resources of a commercial configurable logic device, operating at 100 MHz. With these quite modest resources, it can perform over 9 million lookups/s, while simultaneously processing thousands of updates/s, on databases with over 100000 entries. The lookup structure requires 6.3 bytes per address prefix: less than half that required by other methods. The architecture allows performance to be scaled up by using parallel fast IP lookup (FIPL) engines, which interleave accesses to a common memory interface. This architecture allows performance to scale up directly with available memory bandwidth. We describe the tree bitmap algorithm, our implementation of it in a dynamically extensible gigabit router being developed at Washington University in Saint Louis, and the results of performance experiments designed to assess its performance under realistic operating conditions.

A high-performance JPEG2000 architecture

JPEG2000 is an upcoming compression standard for still images that has a feature set well tuned for diverse data dissemination. These features are possible due to adaptation of the discrete wavelet transform, intra-subband bit-plane coding, and binary arithmetic coding in the standard. We propose a system-level architecture capable of encoding and decoding the JPEG2000 core algorithm that has been defined in Part I of the standard. The key components include dedicated architectures for wavelet, bit plane, and arithmetic coders and memory interfacing between the coders. The system architecture has been implemented in VHDL and its performance evaluated for a set of images. The estimated area of the architecture, in 0.18-/spl mu/ technology, is 3-mm square and the estimated frequency of operation is 200 MHz.

Event-Induced Theta Responses as a Window on the Dynamics of Memory

An important, but often ignored distinction in the analysis of EEG signals is that between evoked activity and induced activity. Whereas evoked activity reflects the summation of transient post-synaptic potentials triggered by an event, induced activity, which is mainly oscillatory in nature, is thought to reflect changes in parameters controlling dynamic interactions within and between brain structures. We hypothesize that induced activity may yield information about the dynamics of cell assembly formation, activation and subsequent uncoupling, which may play a prominent role in different types of memory operations. We then describe a number of analysis tools that can be used to study the reactivity of induced rhythmic activity, both in terms of amplitude changes and of phase variability. We briefly discuss how alpha, gamma and theta rhythms are thought to be generated, paying special attention to the hypothesis that the theta rhythm reflects dynamic interactions between the hippocampal system and the neocortex. This hypothesis would imply that studying the reactivity of scalp-recorded theta may provide a window on the contribution of the hippocampus to memory functions. We review studies investigating the reactivity of scalp-recorded theta in paradigms engaging episodic memory, spatial memory and working memory. In addition, we review studies that relate theta reactivity to processes at the interface of memory and language. Despite many unknowns, the experimental evidence largely supports the hypothesis that theta activity plays a functional role in cell assembly formation, a process which may constitute the neural basis of memory formation and retrieval. The available data provide only highly indirect support for the hypothesis that scalp-recorded theta yields information about hippocampal functioning. It is concluded that studying induced rhythmic activity holds promise as an additional important way to study brain function.

Real-time video decoding scheme for HDTV set-top boxes

We present a scheme for real-time digital HDTV video decoding suitable for DVB or ATSC set-top boxes. Our technique is based on a dual decoding datapath controlled in two fixed-scheduling combinations with an efficient memory interface scheme for anchor pictures. Unlike other decoding approaches such as the slice bar decoding method and the crossing-divided method, our scheme reduces memory access contention problem to achieve real-time HDTV decoding without a high cost in overall decoder buffers, architecture, and bus. Our simulation shows that with a relatively low rate 81 MHz clock, our decoder can decode MPEG-2 MP@HL HDTV in real-time, based on a video format of 1920 /spl times/ 1080 pixels/frame at 30 frames/s, at a bit rate of 18-22 Mbps.

High-speed nuclear quality pulse height analyzer for synchrotron-based applications

A high-throughput pulse height analyzer system for synchrotron-based applications requiring high resolution, high processing speed, and low dead-time has been developed. The system is composed of a 120 ns 12-bit nuclear quality analog-to-digital converter with a self-adaptive fast peak detector stretcher and a custom-made fast histogramming memory module that records and processes the digitized data. The histogramming module is packaged in a VME/VXI compatible interface. Data is transferred through a fast optical link from the memory interface to a computer. A dedicated data acquisition program matches the hardware characteristics of the histogramming memory module. The data acquisition system allows for different data collection modes. The system can acquire data in synchronization with an external trigger or operate as a standard pulse-height analyzer. Acquisition can be performed on several channels simultaneously. A two-channel prototype has been demonstrated at the Stanford Synchrotron Radiation Laboratory accelerator in conjunction with a fluorescence X-ray Absorption Fine Structure Spectroscopy experiment. A detailed description of the entire system is given and experimental data shown.