Memory Interface Research Articles

다수의 프로세싱 유닛 처리를 위한 범용 메모리 제어기의 구조

본 논문은 다수의 프로세싱 유닛의 데이터 처리할 수 있는 메모리 제어기를 설계하였다. 메모리 제어기는 마스터 중재기에 의해 마스터들의 요구 신호를 받아 순서에 맞추어서 데이터 충돌 없이 메모리에 전송하는 역할을 한다. 구현된 메모리 제어기는 마스터 인터페이스, 마스터 중재기, 메모리 인터페이스, 메모리 가속기로 구성된다. 제안한 메모리 제어기는 VHDL을 이용하여 설계하였고, 삼성의 메모리 모델을 이용하여 동작을 검증하였다. FPGA 합성 및 검증을 위해서는 ATERA사의 Quartus II를 이용하였고, 구현된 하드웨어는 Cyclone II 칩을 사용하였다. 시뮬레이션을 위해서는 Cadence사의 ModelSim을 이용하였다. In this paper, we implemented a memory controller which can accommodate data processing blocks. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Interface, Master Arbitrator, Memory Interface, Memory accelerator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used.

In the network

The increasing performance of commodity computer hardware has spawned new use cases for the personal computer. Specialized, cost effective network devices, such as firewalls and intrusion detection systems can be implemented with off the shelf components. At the heart of the performance increase is the computer microarchitecture, comprised of the CPU, peripheral buses and the memory interface. Intel has recently unveiled their next generation core microarchitecture called "Sandy Bridge". In this paper, we present some initial network I/O performance results of the Sandy Bridge microarchitecture platform. The results are compared to the previous Intel microarchitecture, "Nehalem".

ATSC-M/H hardware multiplexer using simple bus arbitration and rate adaptation

In this paper, we present an advanced television systems committee-mobile/handheld (ATSC-M/H) hardware multiplexer for mobile broadcasting services. The entire system consists of a processor, a pre-processor engine, memory, and external interface blocks. Specifically, we address the key design issues such as how to reduce memory access time for handling large amounts of data, how to recover from inaccurate data rates of the legacy ATSC packets, and how to synchronize various function blocks with different data rates. The proposed multiplexer simplifies interface circuits between functional blocks and reduces memory access time through simple bus arbitration. It also provides robustness against inaccurate data rates of the DTV service packets by using a rate adaptation scheme. The preprocessor engine is implemented in an FPGA device and operates at a clock speed of 40 MHz. The proposed system is fully compliant with the ATSC-M/H standard.

Synopsys’ DesignWare DDR PHY compiler eases integration of memory interface IP

Synopsys’ DesignWare DDR PHY compiler eases integration of memory interface IP

IBM POWER7 multicore server processor

The IBM POWER® processor is the dominant reduced instruction set computing microprocessor in the world today, with a rich history of implementation and innovation over the last 20 years. In this paper, we describe the key features of the POWER7® processor chip. On the chip is an eight-core processor, with each core capable of four-way simultaneous multithreaded operation. Fabricated in IBM's 45-nm silicon-on-insulator (SOI) technology with 11 levels of metal, the chip contains more than one billion transistors. The processor core and caches are significantly enhanced to boost the performance of both single-threaded response-time-oriented, as well as multithreaded, throughput-oriented applications. The memory subsystem contains three levels of on-chip cache, with SOI embedded dynamic random access memory (DRAM) devices used as the last level of cache. A new memory interface using buffered double-data-rate-three DRAM and improvements in reliability, availability, and serviceability are discussed

RF/wireless-interconnect: The next wave of connectivity

In the era of the nanometer CMOS technology, due to stringent system requirements in power, performance and other fundamental physical limitations (such as mechanical reliability, thermal constraints, overall system form factor, etc.), future VLSI systems are relying more on ultra-high data rates (up to 100 Gbps/pin or 20 Tbps aggregate), scalable, re-configurable, highly compact and reliable interconnect fabric. To overcome such challenges, we first explore the use of multiband RF/wireless-interconnects which can communicate simultaneously through multiple frequency bands with low power signal transmission, reconfigurable bandwidth and excellent mechanical flexibility and reliability. We then review recent advances in RF/wireless-interconnect in four different potential application domains, which include network-on-chips (NoCs), 3-dimensional integrated circuit (3DIC), advanced memory interface and ultra-high speed contactless connectors. Based on those developments, we further propose the future research direction on future inter- and intra-VLSI interconnect system through the comparison of performance and the proper communication range for all three types of interconnects, including communication data throughput, range and power consumption (pJ/bit) among the RF/wireless-interconnects, the optical interconnects and traditional parallel repeated bus.

Portable cost-effective EEG data acquisition system

Neuro-cognitive dysfunctions are common clinical abnormalities found in society. They require objective analysis by various instruments; an important technique involves monitoring electroencephalogram (EEG) signals. To date, EEG machines have been robust, costly and require patients to come to a hospital for test. Therefore, we have constructed a simple, cheap and portable EEG instrument for wider patient use. It consists of two active digital EEG probes with two channels each, making it a four-channel portable acquisition system. It is further connected through a two-wire serial bus to the acquisition unit, which comprises an analogue to digital converter (ADC) and an ARM board processor with 2 GB memory and USB interface. The whole system is placed in a small box making it highly portable for wider use in clinical settings.

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

In the development of 3D graphic systems for higher resolution and more realistic modeling and rendering, graphic memories also have been playing a critical role to offer the required high bandwidth. Currently, GDDR5 SDRAM's provide with 7Gbps per pin speed [1], reaching their physical limit originated from single-ended signaling nature: noise in reference voltage and power, and channel crosstalk. Especially, the channel crosstalk takes a dominating portion in 7Gbps timing budget, becoming the main barrier for further speed improvement. Although there has been research on crosstalk canceller in memory interface [2], it imposed stringent restrictions on signal ordering and trace length in PCB and package routing, and had limited performance. Therefore, improving the efficiency of DRAM core draws more attention than pin bandwidth now.

Advanced calibration techniques for high-speed source–synchronous interfaces

Advanced and dynamic calibration techniques for maximising the link performance of parallel source–synchronous interfaces are introduced and demonstrated in this study, using as a case study a 533 MHz DDR2 SDRAM memory interface implemented in 90 nm standard complementary metal-oxide-semiconductor (CMOS), whereas most of them have been validated at 800 MHz too. A novel dynamic strobe masking system (DSMS) has also been employed which, in contrast to traditional techniques, adjusts dynamically the length of the masking signal in real time, based on the incoming strobe. Furthermore, optimal data capture is achieved by employing a fast bit-deskew calibration engine, while also a novel I/O calibration scheme is included. Post-layout simulation results demonstrate that the dynamic calibration and skew compensation techniques employed improve the timing margin while providing advanced robustness over process, voltage and temperature variations.

LEVERAGING SHARED CACHES FOR PARALLEL TEMPORAL BLOCKING OF STENCIL CODES ON MULTICORE PROCESSORS AND CLUSTERS

Bandwidth-starved multicore chips have become ubiquitous. It is well known that the performance of stencil codes can be improved by temporal blocking, lessening the pressure on the memory interface. We introduce a new pipelined approach that makes explicit use of shared caches in multicore environments and minimizes synchronization and boundary overhead. Benchmark results are presented for three current x86-based microprocessors, showing clearly that our optimization works best on designs with high-speed shared caches and low memory bandwidth per core. We furthermore demonstrate that simple bandwidth-based performance models are inaccurate for this kind of algorithm and employ a more elaborate, synthetic modeling procedure. Finally we show that temporal blocking can be employed successfully in a hybrid shared/distributed-memory environment, albeit with limited benefit at strong scaling.

DDR2/DDR3 Interface Signal Integrity Analysis Based on IBM Generic Package Model

The data rate of Double Data Rate (DDR) memory interface has become higher, Signal Integrity (SI) analysis is very important for current DDR system design to meet performance requirement. The chip/package types, board level interconnection, driver/receiver modes and power supply network are key factors for the design specification, analysis based on design applications should be performed to evaluate delay, reflection, jitter, simultaneous switching power noise, timing budget for the DDR system. This paper presents the method of performing DDR2/DDR3 interface SI simulation by using IBM Generic Package Model (GPM).

Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23× times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89 percent of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility/performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

Automatic Generation of Memory Interfaces for ASIPs

With the growing market for multi-processor system-on-chip (MPSoC) solutions, application-specific instruction-set processors (ASIPs) gain importance as they allow for a wide tradeoff between flexibility and efficiency in such a system. Their development is aided by architecture description languages (ADLs) supporting the automatic generation of architecture-specific tool sets as well as synthesizable register transfer level (RTL) implementations from a single architecture model. However, these generated implementations have to be manually adapted to the interfaces of dedicated memories or memory controllers, slowing down the design-space exploration regarding the memory architecture. To overcome this drawback, the authors extend RTL code generation from ADL models with the automatic generation of memory interfaces. This is accomplished by introducing a new abstract and versatile description format for memory interfaces and their timing protocols. The feasibility of this approach is demonstrated in real-life case studies, including a design space exploration for a banked memory system.

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data

Applications based on Discrete Fourier Transforms (DFT) are extensively used in various areas of signal and digital image processing. Of particular interest is the two-dimensional (2D) DFT which is more computation- and bandwidth-intensive than the one-dimensional (1D) DFT. Traditionally, a 2D DFT is computed using Row-Column (RC) decomposition, where 1D DFTs are computed along the rows followed by 1D DFTs along the columns. Both application specific and reconfigurable hardware have been used for high-performance implementations of 2D DFT. However, architectures based on RC decomposition are not efficient for large input size data due to memory bandwidth constraints. In this paper, we propose an efficient architecture to implement the 2D DFT for large-sized input data based on a novel 2D decomposition algorithm. This architecture achieves very high throughput by exploiting the inherent parallelism due to the algorithm decomposition and by utilizing the row-wise burst access pattern of the external memory. A high throughput memory interface has been designed to enable maximum utilization of the memory bandwidth. In addition, an automatic system generator is provided for mapping this architecture onto a reconfigurable platform of Xilinx Virtex5 devices. For a 2K×2K input size, the proposed architecture is 1.96x times faster than RC decomposition based implementation under the same memory constraints, and also outperforms other existing implementations.

Light-weight salient foreground detection for embedded smart cameras

An embedded smart camera is a stand-alone unit that not only captures images, but also includes a processor, memory and communication interface. Battery-powered, embedded smart cameras introduce many additional challenges since they have very limited resources, such as energy, processing power and memory. Computer vision algorithms running on these camera boards should be light-weight and efficient. Considering the memory requirements of an algorithm and its portability to an embedded processor should be an integral part of the algorithm design in addition to the accuracy requirements. This paper presents a light-weight and efficient background modeling and foreground detection algorithm that is highly robust against lighting variations and non-static backgrounds including scenes with swaying trees, water fountains and rain. Compared to many traditional methods, the memory requirement for the data saved for each pixel is very small in the proposed algorithm. Moreover, the number of memory accesses and instructions are adaptive, and are decreased depending on the amount of activity in the scene. Each pixel is treated differently based on its history, and instead of requiring the same number of memory accesses and instructions for every pixel, we require less instructions for stable background pixels. The plot of the number of unstable pixels at each frame also serves as a tool to find the video portions with high activity. The proposed method selectively updates the background model with an automatically adaptive rate, thus can adapt to rapid changes. As opposed to traditional methods, pixels are not always treated individually, and information about neighbors is incorporated into decision making. The results obtained with nine challenging outdoor and indoor sequences are presented, and compared with the results of different state-of-the-art background subtraction methods. The ROC curves and memory comparison of different background subtraction methods are also provided. The experimental results demonstrate the success of the proposed light-weight salient foreground detection method.

A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling

This paper presents a 4.3 GB/s mobile memory interface that utilizes low power states with rapid transition times to support power efficient signaling over a wide range of effective bandwidths. The fastest power state transition is implemented by a global synchronous clock pause that gates dynamic power consumption without any loss of system state. Extensive use of CMOS circuit topologies, with low static power consumption, provides maximum power savings when the clocks are paused. The memory controller forwards a half bit-rate clock to the memory for synchronous communication, which is similarly paused in the low power state. Thus, dynamic interface power on the memory itself naturally responds to the clock pausing, without any explicit communication from the controller or special low-power state on the memory. Low-swing differential signaling based on a push-pull voltage mode driver results in good signal integrity and power efficiency at peak activity. Test-chips fabricated in a 40 nm low-power CMOS technology achieve 3.3 mW/Gb/s power efficiency at 4.3 GB/s data bandwidth, and support better than 5 mW/Gb/s operation over a range from 0.03 to 4.3 GB/s.

SoC의 성능 향상을 위한 크로스바 스위치 온칩 버스 설계

기존에 사용되는 대부분의 SoC는 공유버스 구조를 가지고 있어, 병목현상이 발생하는 문제점을 가지고 있다. 이러한 문제점은 SoC의 내부의 IP 수가 많을수록, 전체적인 SoC의 성능을 저하시키게 되어, CPU 자체의 속도보다는 전체적인 통신 분배에 의해 SoC의 성능이 좌우 된다. 본 논문에서는 공유버스의 단점인 병목현상을 줄이고 SoC의 성능을 향상시키기 위해 크로스바 스위치버스 구조를 제안한다. 크로스바 스위치 버스는 마스터 모률 8개, 슬레이브 모듈 16개까지 연결이 가능하며, 다중 버스 채널구조로 되어 있어 병렬통신이 가능하다. 또한 각 16개의 슬레이브 인터페이스마다 우선순위 정보가 저장된 아비터가 내장되어 하나의 마스터가 슬레이브를 독점하는 것을 방지하는 것과 동시에 효율적인 통신을 지원한다. OpenRISC 프로세서, VGA/LCD 제어기, AC97 제어기, 디버그 인터페이스, 메모리 인터페이스로 구성되는 SoC 플랫폼의 WISHBONE 온칩 공유버스 구조와 크로스바 스위치 버스구조의 성능을 비교한 결과, 기존의 공유버스보다 26.58%의 성능이 향상되었다. Most of the existing SoCs have shared bus architecture which always has a bottleneck state. The more IPs are in an SOC, the less performance it is of the SOC, Therefore, its performance is effected by the entire communication rather than CPU speed. In this paper, we propose cross-bar switch bus architecture for the reduction of the bottleneck state and the improvement of the performance. The cross-bar switch bus supports up to 8 masters and 16 slaves and parallel communication with architecture of multiple channel bus. Each slave has an arbiter which stores priority information about masters. So, it prevents only one master occupying one slave and supports efficient communication. We compared WISHBONE on-chip shared bus architecture with crossbar switch bus architecture of the SOC platform, which consists of an OpenRISC processor, a VGA/LCD controller, an AC97 controller, a debug interface, a memory interface, and the performance improved by 26.58% than the previous shared bus.

Power7: IBM's Next-Generation Server Processor

The Power7 is IBM's first eight-core processor, with each core capable of four-way simultaneous-multithreading operation. Its key architectural features include an advanced memory hierarchy with three levels of on-chip cache; embedded-DRAM devices used in the highest level of the cache; and a new memory interface. This balanced multicore design scales from 1 to 32 sockets in commercial and scientific environments.

Correction on “A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232

The authors of the above titled article (ibid., vol. 44, no. 8, pp. 2222-2232, Aug. 09) acknowledge the contribution from an earlier paper.

1P1-G20 リソースを活用した移動ロボットの提案

In this paper, we propose a method to construct robot by utilizing resource in notebook personal computer. To develop a mobile robot, various components in areas of mechanics, electronics and computer control should be prepared. Meanwhile, usual personal computer already has almost components to build a mobile robot. For example, CPU, memory, battery and user interface are already included. Just mobility is not included. Then, we propose a USB motor device to develop a mobile robot by utilizing resource. To use such device, we can develop a mobile robot easily. We describe how to develop the device and confirm the effectiveness of our method through a experiment.