Memory Interface Research Articles

SLDRAM: high-performance, open-standard memory

The primary objective of DRAM-dynamic random access memory-is to offer the largest memory capacity at the lowest possible cost. Designers achieve this by two means. First, they optimize the process and the design to minimize die area. Second, they ensure that the device serves high-volume markets and can be mass-produced to achieve the greatest economies of scale. SLDRAM-synchronous-link DRAM-is a new memory interface specification developed through the cooperative efforts of leading semiconductor memory manufacturers and high-end computer architects and system designers. SLDRAM meets the high data bandwidth requirements of emerging processor architectures and retains the low cost of earlier DRAM interface standards. These and other benefits suggest that SLDRAM will become the mainstream commodity memory of the early 21st century.

Synchronization and communication in the T3E multiprocessor

This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the rationale behind changes made for the T3E. We include performance measurements for various aspects of communication and synchronization.The T3E augments the memory interface of the DEC 21164 microprocessor with a large set of explicitly-managed, external registers (E-registers). E-registers are used as the source or target for all remote communication. They provide a highly pipelined interface to global memory that allows dozens of requests per processor to be outstanding. Through E-registers, the T3E provides a rich set of atomic memory operations and a flexible, user-level messaging facility. The T3E also provides a set of virtual hardware barrier/eureka networks that can be arbitrarily embedded into the 3D torus interconnect.

Synchronization and communication in the T3E multiprocessor

This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have learned from the T3D project (the predecessor to the T3E) and the rationale behind changes made for the T3E. We include performance measurements for various aspects of communication and synchronization.The T3E augments the memory interface of the DEC 21164 microprocessor with a large set of explicitly-managed, external registers (E-registers). E-registers are used as the source or target for all remote communication. They provide a highly pipelined interface to global memory that allows dozens of requests per processor to be outstanding. Through E-registers, the T3E provides a rich set of atomic memory operations and a flexible, user-level messaging facility. The T3E also provides a set of virtual hardware barrier/eureka networks that can be arbitrarily embedded into the 3D torus interconnect.

The Design and Performance Evaluation of the DI-Multicomputer

In this paper, we propose a new multicomputer node architecture, theDI-multicomputerwhich uses packet routing on a uniform point-to-point interconnect for both local memory access and internode communication. This is achieved by integrating a router into each processor chip and eliminating the memory bus interface. Since communication resources such as pins and wires are allocated dynamically via packet routing, the DI-multicomputer is able to maximize the available communication resources, providing much higher performance for both intranode and internode communication. Multi-packet handling mechanisms are used to implement a high performance memory interface based on packet routing. The DI-multicomputer network interface provides efficient communication for both short and long messages, decoupling the processor from the transmission overhead for long messages while achieving minimum latency for short messages. Trace-driven simulations based on a suite of message passing applications show that the communication mechanisms of the DI-multicomputer can achieve up to four times speedup when compared to existing architectures.

LIGHTNING network and systems architecture

This paper describes a hierarchical WDM-based optical network testbed project that is being constructed to interconnect a large number of high performance computers to create a distributed shared memory environment. The objective of the architecture is to achieve scalability yet avoid the requirement of multiple wavelength tunable devices per node. It is a singlehop all-optical network; a packet remains in the optical form from source to destination. It features wavelength channel reuse at each level, allowing scalability to very large system sizes. It partitions the traffic between different levels of the hierarchy without electronic intervention in a combination of wavelength-division and space-division multiplexing. A significant advantage of this approach is its ability to vary dynamically the bandwidth provided to different levels of the hierarchy. Each node monitors the traffic intensities on each channel and can detect any temporal or spatial shift in traffic balance. LIGHTNING can dynamically reconfigure to balance the traffic at each level by reassigning wavelengths associated with each level in the hierarchy to a higher or lower level depending on need. Bandwidth reallocation is completely decentralized, achieving highly fault tolerant system behavior. This paper describes the system architecture, and the network and memory interface that have been developed in this project.

Superscalar instruction issue in an asynchronous microprocessor

The implementation of the instruction issuer for a superscalar asynchronous microprocessor (SCALP) is described as a case study in asynchronous design. The issuer accepts five instructions at a time from the memory interface and issues them out of order to five parallel functional units. SCALP's architecture is designed to reduce the complexity of the instruction issuer by removing the need to detect dependencies between instructions as they are issued. The design has a regular cellular structure suitable for VLSI implementation. The issue's performance is sufficient that no bottleneck forms in the SCALP pipeline.

SyncLink: high-speed DRAM for the future

In 1987 it was becoming apparent that computer systems would need to communicate at data rates beyond the capabilities of then current approaches. To take on this challenge, the IEEE Futurebus group formed a new group dedicated to building a fast, coherent interface, scalable from the smallest computer to the largest mainframe. The IEEE officially established the SCI (Scalable Coherent Interface) working group, referenced as IEEE P1596, in 1988. Today the SCI is IEEE Std 1596. It has several derivatives that enhance its operation and meet additional needs such as real-time operations: a differential voltage specification (IEEE 1536.3), a point-to-point memory interface (IEEE 1596.4), and SyncLink (IEEE P1596.7). SyncLink is a new, high-speed memory interface that combines synchronous dynamic RAM (SDRAM), developed in the late 1980s, and the IEEE's RamLink interface, developed in 1990. SyncLink uses the earlier interface's packet protocol as a base but eliminates its point-to-point link to reduce latency. The new interface uses SDRAM's internal pipelining and control for efficient bus utilization. It allows access in the lowest latency possible for a very high bandwidth DRAM. Future plans include data rates of 800 Mbits per pin per second in 1998, to double in the early 2000s. This rate will allow systems to operate at full capability, even when running 3D graphics.

A single chip video signal processing architecture for image processing, coding, and computer vision

A new VLSI (CMOS) architecture for an internally multiprocessing, single chip, SIMD-based video signal processor (VSP) is presented. The limitations of extended DSP architectures and conventional array processors are discussed in the context of image processing, coding and computer vision. How this gives rise to the architecture is described. Architectural flexibility is provided by the integration of a novel array-based processing core, together with a RISC processor, intelligent memory interface processor, and internal cache RAM. The array core architecture is a second generation, enhanced array whose key features are: 2 b datapath, dual processor mesh-connected array planes and combined SIMD/systolic functionality. The core is optimized for 2-D windowed operations, particularly 2-D multiply-accumulation and transforms. The device is expected to operate at 80 MHz on low voltage silicon and deliver real-time performance across a range of target applications. >

Distributed control architecture for a sensor-driven dual arm system

A distributed computing and control architecture for sensor-based control of a dual arm system is described. The system comprises of two PUMA 560 robots with state-of-the-art joint-level motion controllers with accurate joint position and velocity measurement, an accurate joint calibration system, and six-axis wrist force/torque sensors with optical fiber communication with the controller. A Silicon Graphics workstation, through a shared memory interface with the joint-level controllers, provides a task-level command and control capability. A computer vision system, with two CCD (Charge-Coupled Device) cameras, is also interfaced to the workstation. A variety of control schemes may be implemented on this system. A servo rate of 1000 Hz, without interpolation, has been achieved for task-level servo schemes with force feedback. The experimental results presented here demonstrate the performance capabilities of the system.

Hardware support for error detection in multiprocessor systems — a case study

A comparison of the most important methods for error detection in multiprocessor systems is presented based upon the experiences gained in the development of the fault-tolerant multiprocessor system MEMSY. A detailed comparison between watchdog processors and master-checker type duplication based fault tolerance is given, from the point of view of fault coverage, hardware and time overhead. It is shown that a simple multiplication in itself is insufficient to assure proper error detection features, especially if a low error latency time is required. Design guidelines are presented for the effective use of the duplication, based on the master-checker mode. Additionally a new general purpose watchdog processor architecture is proposed, which monitors the behaviour of the main processor by checking the control flow of processes using an extended signature integrity checking (ESIC) method. The watchdog processor is independent of the architecture of the main processor because it is linked to the main processor by a memory interface. The watchdog processor is convenient for multiprocessor systems based on standard components and a RISC/CISC processor with large cache as node processor.

A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture

Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving input buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >

The Image chip for high performance 3D rendering

The Image chip, which accelerates 3D rendering algorithms base on Bresenham's line drawing and Pineda's parallel polygon drawing algorithms, is discussed. With these algorithms, Image can directly draw lines, spans, and triangles in wireframe, hidden-line, and Gouraud-shading modes. Image also directly antialiases vectors or provides antialiasing information to enhance antialiasing of vectors or triangles. Image's operation, separation into layers to maximize performance and simplify the input and output interfaces, and support of advanced rendering effects such as Phong shading and texture mapping are described. The designs of Image's internal architecture, host interface, and memory interface are also described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

IMAP: INTEGRATED MEMORY ARRAY PROCESSOR

This paper presents architectural features and performances for an Integrated Memory Array Processor (IMAP) LSI, which integrates a large capacity memory and a one-dimensional SIMD processor array on a single chip. The IMAP has a conventional memory interface, almost the same as a dual port video RAM with operational input extension. SIMD processing is carried out on the IMAP chip, using an internal processor array, while other higher level processing is concurrently accomplished with external processors through the random access memory port. In addition to the basic IMAP architecture, this paper describes orthogonal IMAP, which has an extended IMAP architecture. The basic IMAP uses a conventional memory cell, while the orthogonal IMAP uses an orthogonal memory for holding images.

A digital audio signal processor for sound field controls

A new digital audio signal processor (DASP) that is suitable for sound field control applications has been developed. An adaptable external memory configuration method is introduced. The device includes a 32-bit arithmetic and logic unit (ALU) and a 32* 24 bit multiplier/accumulator. The processor is designed to optimize sound field controls such as sound field reproduction of concert halls in a listening room or sound position selection to create natural stereo sounds in an automobile. The programmable external memory interface allows various configurations of DRAM to be selected. The DASP with the external memory interface allows implementation of sound field control, equalization, and filtering applications on a single chip. This reduces overall system costs and periods of system development.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A multichannel, high linearity current digitizer for digital subtraction angiography

An experiment studying the application of synchrotron radiation for transvenous coronary angiography requires special electronics to read out a 600-element Si(Li) detector. To obtain high image quality, the electronic system must digitize the current in all 600 elements every 2 ms with a dynamic range of 40000 and a maximum nonlinearity of 0.02%. Each channel of electronics contains a current-to-voltage amplifier with computer-controlled gain and offset followed by a voltage-to-frequency converter used in the reciprocal counting mode. A high-speed digital readout method using a lookup table, digital multiplier and direct memory interface was developed. The entire system has been designed to have a low cost per channel and to be easily expanded by 1200 signal channels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fault tolerance in N-MOS random access memories with dynamic redundancy methods

In this paper two methods of dynamic redundancy are discussed which allow the treatment of memory chip faults at the interface of the main memory. The first approach is a standby system where the I/O lines of the memory can be dynamically switched to spare bit slices. This task is performed by a switching network implemented at the memory interface. Every memory access is controlled by a fault status table (FST) which memorizes the fault conditions of each memory block. This fault status table is also implemented outside the memory system. The basic properties of the proposed methods and a prototype VLSI implementation are discussed. Then a corresponding method for memory reconfiguration by means of graceful degradation is discussed. The memory reliabilities implied by both the methods are estimated. These two methods have considerable importance in reliability when compared to conventional methods. The major advantage is that the size of reconfiguration of the system can be considerably reduced.

A digital signal processor for digital audio use

The authors describe the D/sup 2/SP digital signal processor which is designed with a dual processor architecture, and is especially effective for stereo audio signal processing. The D/sup 2/SP has two independent processor units, the left processor and right processor. The D/sup 2/SP contains an audio data interface, external dynamic random-access memory (DRAM) interface, microcomputer interface, and a sequence controller. The single chip D/sup 2/SP is capable of performing audio signal processing needed for graphic equalizers, surround, and sound power spectrum calculation. The dual processor mainly consists of a 24-bit multiplier with a 108-ns cycle time and is assembled on a single chip fabricated from 1.2- mu m CMOS technology. The total number of integrated transistors is approximately 300 K. Applications, such as use as a seven-band graphic equalizer, seven-band power spectrum calculator, and surround sound processing, are briefly discussed. >

Systolic arrays for Viterbi processing in communication systems with a time-dispersive channel

The theory and design of systolic arrays for Viterbi processing in communication systems with a time-dispersive time-varying channel is discussed. The architecture, algorithms, and processor elements, for a two-dimensional systolic array are described. The array supports the branch metric computations required for an adaptive Viterbi processor. The array is designed so that computations propagate along the rows of the array, while data symbols propagate along the columns. All interprocessor data flow and connections within the array are nearest-neighbor. The array illustrates how the Viterbi-processor algorithms can be structured to achieve a high degree of computational concurrency. Variations in the array design are described and evaluated in terms of computational resource requirements and utilization and computational throughput. A high-bandwidth memory interface is proposed, and system design considerations are discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of array processor software for nonlinear structural analysis

This paper presents an investigation of the solution of large-scale nonlinear structural problems using a 32-bit minicomputer with an attached 64-bit array processor. The two processors communicate via a common memory interface. A user-oriented software package has been designed to allow the use of the given computer configuration by a typical engineer or a scientist. It is possible to use the system without a detailed knowledge of the operation of the hardware and the complex data handling necessary to manipulate the data associated with a large problem. Several test examples are considered using finite element 3-D frame models and the Newton-Raphson solution scheme. The array processor could not be utilized as yet, due to the lack of the proper vendor software. Hence, a simulator was designed to predict the system performance.

Memory interface for the 2650 microprocessor

The memory is an indispensible part of a microprocessor system and has a considerable influence on the system design. The type of memory to be used and the method of interfacing with the microprocessor must be chosen during the early design stages. This article describes a number of memory interface examples using the Signetics 2650 microprocessor. Detailed information about these memory systems can be found in the application notes of the 2650 microprocessor published by Signetics. There is an extensive choice of semiconductor memories: ROM, PROM, EPROM, RAM static and RAM dynamic. ROM can be used economically as program storage in systems which are produced in large quantities. PROM and EPROM are suitable as program storage in systems which are produced in small quantities. EPROM is especially attractive in the software development phase, or in systems where program changes are expected. RAM will generally be used as working storage. The capacity required is entirely dependent upon the application. For capacities lower than 4k bytes, static RAM may be used. For larger capacities, dynamic RAM is a more economical choice, although an extra memory refresh circuit is necessary. Three items must be considered for the interface design: • - logic level compatibility • - load and drive capability • - timing. The hardware requirement is greatly simplified by the high degree of compatibility between the microprocessor and memories.