Hardware support for error detection in multiprocessor systems — a case study

Abstract

A comparison of the most important methods for error detection in multiprocessor systems is presented based upon the experiences gained in the development of the fault-tolerant multiprocessor system MEMSY. A detailed comparison between watchdog processors and master-checker type duplication based fault tolerance is given, from the point of view of fault coverage, hardware and time overhead. It is shown that a simple multiplication in itself is insufficient to assure proper error detection features, especially if a low error latency time is required. Design guidelines are presented for the effective use of the duplication, based on the master-checker mode. Additionally a new general purpose watchdog processor architecture is proposed, which monitors the behaviour of the main processor by checking the control flow of processes using an extended signature integrity checking (ESIC) method. The watchdog processor is independent of the architecture of the main processor because it is linked to the main processor by a memory interface. The watchdog processor is convenient for multiprocessor systems based on standard components and a RISC/CISC processor with large cache as node processor.