Abstract
The implementation on hardware of the first layer of Kanerva's sparse distributed memory (SDM) is presented in this work. The hardware consist on a co-processor board for connection on ISA standard bus of an IBM–PCcompatible computer. The board, named reconfigurable co-processor for SDM(RC-SDM), comprises on Xilinx FPGAs, local random access memory and bus interface circuits. Based on in-system reconfiguration capacity of FPGAs, RC-SDM easily allows change of the characteristics of SDM topology implemented. First results show a speed-up of four times of RC-SDM in relation to a software implementation of the algorithm.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
