Abstract
The implementation on hardware of the first layer of Kanerva's sparse distributed memory (SDM) is presented in this work. The hardware consist on a co-processor board for connection on ISA standard bus of an IBM–PCcompatible computer. The board, named reconfigurable co-processor for SDM(RC-SDM), comprises on Xilinx FPGAs, local random access memory and bus interface circuits. Based on in-system reconfiguration capacity of FPGAs, RC-SDM easily allows change of the characteristics of SDM topology implemented. First results show a speed-up of four times of RC-SDM in relation to a software implementation of the algorithm.
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