Memory Device Structure Research Articles

Emerging Robust Polymer Materials for High-Performance Two-Terminal Resistive Switching Memory.

Facing the era of information explosion and the advent of artificial intelligence, there is a growing demand for information technologies with huge storage capacity and efficient computer processing. However, traditional silicon-based storage and computing technology will reach their limits and cannot meet the post-Moore information storage requirements of ultrasmall size, ultrahigh density, flexibility, biocompatibility, and recyclability. As a response to these concerns, polymer-based resistive memory materials have emerged as promising candidates for next-generation information storage and neuromorphic computing applications, with the advantages of easy molecular design, volatile and non-volatile storage, flexibility, and facile fabrication. Herein, we first summarize the memory device structures, memory effects, and memory mechanisms of polymers. Then, the recent advances in polymer resistive switching materials, including single-component polymers, polymer mixtures, 2D covalent polymers, and biomacromolecules for resistive memory devices, are highlighted. Finally, the challenges and future prospects of polymer memory materials and devices are discussed. Advances in polymer-based memristors will open new avenues in the design and integration of high-performance switching devices and facilitate their application in future information technology.

Asymmetric Electrode Work Function Customization via Top Electrode Replacement in Ferroelectric and Field‐Induced Ferroelectric Hafnium Zirconium Oxide Thin Films

AbstractNon‐volatile memory device structures such as ferroelectric random‐access memory and ferroelectric tunnel junctions employ switchable spontaneous polarization to hold binary states. These devices can potentially benefit from the imposition of spontaneous internal biases and their resulting effect on the polarization properties of the ferroelectric (or field‐induced ferroelectric/antiferroelectric) layer. While HfO2‐based thin films are ideal candidates for implementation into these devices due to their scalability and silicon compatibility, the phase purity of these oxides is sensitive to the selection of electrode material, preventing incorporation of asymmetric electrode layers into such structures. Within this work, electrode replacement following post‐metallization anneal processing is introduced as a route to achieve ferroelectric and field‐induced ferroelectric HfxZr1−xO2 (HZO) thin films with electrode‐independent phase constitutions. The effects of this process and the corresponding internal biases imposed across the HZO layers due to asymmetric work functions are investigated. It is shown that internal biases vary in magnitude in accordance with prediction based on the work functions of the replaced electrode layers and affect remanent polarization magnitudes. Accordingly, electrode replacement presents a processing route that can readily produce HZO films with spontaneous internal biases and electrode‐independent phase constitutions, facilitating implementation of these ferroelectrics into the next generation device structures.

Recent advances in organic‐based materials for resistive memory applications

AbstractWith the rapid development of data‐driven human interaction, advanced data‐storage technologies with lower power consumption, larger storage capacity, faster switching speed, and higher integration density have become the goals of future memory electronics. Nevertheless, the physical limitations of conventional Si‐based binary storage systems lag far behind the ultrahigh‐density requirements of post‐Moore information storage. In this regard, the pursuit of alternatives and/or supplements to the existing storage technology has come to the forefront. Recently, organic‐based resistive memory materials have emerged as promising candidates for next‐generation information storage applications, which provide new possibilities of realizing high‐performance organic electronics. Herein, the memory device structure, switching types, mechanisms, and recent advances in organic resistive memory materials are reviewed. In particular, their potential of fulfilling multilevel storage is summarized. Besides, the present challenges and future prospects confronted by organic resistive memory materials and devices are discussed.image

Switching and synaptic characteristics of AZO/ZnO/ITO valence change memory device

This paper reports the resistive switching and synaptic capability of AZO/ZnO/ITO transparent and flexiblevalence change memory device structure. The device performs stable endurance for more than 50 cycles with sufficient ON/OFF ratio of one order of magnitude; no intermediate state (data error) is observed during the cycle-to-cycle test. By exploiting the analog switching characteristic of the device and employing identical pulses to the top electrode, a synaptic behavior can be achieved. A low programming voltage of 1.5V is used to modulate the conductance during potentiation and depression which indicate that the device is a logic-compatible. The conduction mechanism during the switching processand the device performance is discussed.

Characterization of Au/PbTi0.5Fe0.5O3/Si structure for possible multiferroic based non-volatile memory applications

Magnetoelectric multiferroic PbTi0.5Fe0.5O3 films are deposited on a ⟨100⟩ conducting p-Si substrate without any buffer layer by using pulsed laser deposition and characterized for possible non-volatile memory applications. Their crystalline structure and surface morphology were characterized by using x-ray diffraction and AFM techniques. HRTEM was employed to determine the film–substrate interface. The electronic structure of the film was investigated by XPS, and no signature of metal was found for all the elements. The chemical shift of the Ti 2p XPS peak is attributed to the replacement of Ti with Fe in the PbTiO3 matrix. Piezoelectric force microscopy (PFM) results indicate the 180° phase shift of ferroelectric polarization. The upward self-polarization phenomenon is also observed in the PFM study. Magnetic and magneto-electric coupling measurements were carried out to confirm the magnetic nature and electro-magnetic coupling characteristics. C–V measurements exhibit clock-wise hysteresis loops with a maximum memory window of 1.2 V and a sweep voltage of ±7 V. This study could influence the fabrication of silicon compatible multiple memory device structures.

Evaluating Resistive Memory Devices for Neuromorphic Computing Using Ultrashort Voltage Pulses

A special purpose neural algorithm accelerator based on resistive memory could potentially reduce the energy requirements of neural algorithm implementation by six orders of magnitude over conventional general purpose GPU/CPU hardware (1). The device requirements for such a neural algorithm accelerator depend on attributes including write variability, write linearity, and read noise, as described in reference (2). Devices with multiple resistance states accessible via symmetric voltage pulses of constant magnitude are highly desired for neuromorphic hardware implementations. Tantalum oxide resistive memory devices have been previously shown to have low energy requirements and better control of conductivity during switching in the ultrashort time domain (3). We will report on how employing voltage pulses with ultrashort pulse widths allow for finer control of tantalum oxide based device conductance change per pulse (ΔG/G) unlocking additional neuromorphic states. A parameter space of pulse voltage and time is used to elucidate switching kinetics and switching energy expenditure during device operation. Lastly, the performance of several different resistive memory device structures will be comparatively evaluated for suitability in implementing a neural algorithm accelerator. This work was supported by Sandia National Laboratories’ Laboratory Directed Research and Development (LDRD) Program under the Hardware Acceleration of Adaptive Neural Algorithms Grand Challenge. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000. REFERENCES: 1. Kadetotad, Deepak, et al. "Parallel architecture with resistive crosspoint array for dictionary learning acceleration." IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5.2 (2015): 194-204. 2. S. Agarwal, et. al. “Resistive Memory Device Requirements for a Neural Algorithm Accelerator,” International Joint Conference on Neural Networks, (2016) 3. Strachan, John Paul, et al. “Measuring the switching dynamics and energy efficiency of tantalum oxide memristors” Nanotechnology22.50 (2011): 505402. Figure 1

Observation of conductive filaments in a resistive switching nonvolatile memory device based on amorphous InGaZnO thin films

Resistive switching mechanism was investigated on a model nonvolatile memory device structure composed of an amorphous InGaZnO (a-IGZO) insulator layer and TiN and indium tin oxide (ITO) electrodes by directly observing the microstructural and compositional changes in the device during the switching operation. In the pristine state, microstructure of the device was characterized by well-defined smooth interface between the a-IGZO switching layer and electrodes. Once the device is in a set state by applying positive bias to the TiN electrode, the TiN/a-IGZO interface became markedly rough with irregularly localized structures protruded into the a-IGZO layer from the TiN electrode. Transmission electron microscopy revealed that these protruded structures are polycrystalline TiN which have been formed by the migration of Ti species during the voltage sweep due to the electric field between positively biased TiN and grounded ITO electrodes. The device structures showed bistable unipolar switching behavior while they were transparent to visible light with reasonable transmittance of about 77%.

Thickness dependence of the resistive switching behavior of nonvolatile memory device structures based on undoped ZnO films

The resistive switching behavior of Al/ZnO/Al layered memory device structures was investigated in connection with varying ZnO layer thickness and related changes in crystallinity and concentration of oxygen-related defects. It was observed that, with increasing thickness, the crystallinity of the ZnO layer was improved and the concentration of oxygen-related defects within the layer increased. While the device showed unipolar switching characteristics, the current–voltage hysteresis was dependent on the thickness of the ZnO layer. In particular, the set voltage gradually increased with increasing layer thickness in the high resistive state whereas the reset voltage remained almost constant in the low resistive state. The observed operation characteristics of the device structures in relation to the crystallinity and oxygen-related defect concentration of the ZnO layer suggest that extended defects such as grain boundaries and dislocations play important roles in determining device performances.

Low power resistive switching memory using Cu metallic filament in Ge 0.2Se 0.8 solid-electrolyte

Bipolar resistive switching memory device using Cu metallic filament in Au/Cu/Ge 0.2Se 0.8/W memory device structure has been investigated. This resistive memory device has the suitable threshold voltage of V th > 0.18 V, good resistance ratio ( R High/ R Low) of 2.6 × 10 3, good endurance of >10 4 cycles with a programming current of 0.3 mA/0.8 mA, and 5 h of retention time at low compliance current of 10 nA. The low resistance state ( R Low) of the memory device decreases with increasing the compliance current from 1 nA to 500 μA for different device sizes from 0.2 μm to 4 μm. The memory device can work at very low compliance current of 1 nA, which can be applicable for extremely low power-consuming memory devices.

Resistance Switching and Formation of a Conductive Bridge in Metal/Binary Oxide/Metal Structure for Memory Devices

The resistance switching mechanism of a metal/CuO/metal sandwich with a planar device structure has been studied. We report the direct observation of a conducting bridge within the CuO channel of the device, which is formed upon the initial voltage application (forming process). It is found that the resistance switching phenomenon only occurs when just a single bridge is formed during a soft dielectric breakdown. We argue that the reduction and oxidation of this conducting bridge by the action of an applied field and/or current gives rise to a novel nonvolatile memory effect.

Synthesis and Electronic Application of Germanium Nanocrystals in Silicon Oxide Matrix

ABSTRACTThe size of germanium (Ge) nanocrystals in a trilayer memory device structure was controlled by varying the thickness of the middle co-sputtered Ge plus silicon oxide layer. Such confinement of nanocrystals was not effective in a trilayer structure with a pure Ge middle layer. Significant diffusion of Ge atoms through the tunnel oxide or rapid thermal oxide (RTO) layer and into the silicon substrate was observed when the RTO layer thickness of the trilayer structure was reduced. This resulted in no (or very few) nanocrystals formed in the system. A higher charge storage capability was obtained from devices with a thinner RTO layer.

Electrical properties of metal-oxide semiconductor nano-particle device

We have studied the electrical transport properties of two types of devices utilizing metal-oxide semiconductor nano-particles, Cu 2O and Fe 2O 3. The metal-oxide nano-particles are embedded in a polyimide matrix through chemical reaction between the metal thin film and polyamic acid as a precursor of polyimide. To test the electron tunneling via nano-particles, Au nano-electrodes are fabricated on a SiO 2/Si substrate with a 30 nm gap by electron-beam lithography. A single electron tunneling behavior was apparent in the devices with Cu 2O nano-particle inserted into the nano-gap electrodes. Also, a memory effect was measured in a floating-gated memory device structure with Fe 2O 3 nano-particles embedded in a polyimide matrix.

Growth of (103) fiber-textured SrBi2Nb2O9 films on Pt-coated silicon

(103) fiber-textured SrBi2Nb2O9 thin films have been grown on Pt-coated Si substrates using a SrRuO3 buffer layer. High-resolution transmission electron microscopy reveals that the fiber texture arises from the local epitaxial growth of (111) SrRuO3 grains on (111) Pt grains and in turn (103) SrBi2Nb2O9 grains on (111) SrRuO3 grains. The films exhibit remanent polarization values of 9 μC/cm2. The uniform grain orientation (fiber texture) should minimize grain-to-grain variations in the remanent polarization, which is important to continued scaling of ferroelectric memory device structures.

Fatigue Properties of Lanthanum Strontium Manganate–lead Zirconate Titanate Epitaxial Thin Film Heterostructures Produced by a Chemical Solution Deposition Method

A liquid-precursor process was used to produce an epitaxial all-oxide ferroelectric memory device structure. The lanthanum strontium manganate–lead zirconate titanate–lanthanum strontium manganate (LSMO–PZT–LSMO) structure used for this device shows excellent polarization and fatigue behavior with a remnant polarization Pr of 42 µC/cm2 and a coercive field Ec of 68 keV. The polarization was found to only slightly degrade after over 1010 fatigue cycles. This behavior is contrasted with epitaxial PZT using a metal top electrode. In addition, the use of a top LSMO electrode was a sufficient barrier to Pb loss during heating to allow subsequent (or prolonged) heat treatments that would generally lead to Pb loss.

Effects of surface topography on oxide deposition rates using TEOS/O[sub 2] chemistry

The effect of surface topography on TEOS/O2 oxide deposition rates is investigated. It is found that the oxide thickness is significantly less on the top layers of topography used in static random access memory device structures compared to flat wafers for fixed conditions of power, flow, and pressure. The total mass deposition increases, however, in the presence of topography. These effects can be understood from the perturbation on the precursor radical densities near the surface caused by the surface topography. A simple model based on the diffusion-reaction equation with an appropriate boundary condition is proposed to explain the effect. The boundary condition is developed as an effective macroscopic reflection coefficient that takes into account trapping effects of film precursors in the topography. The application of the model to the experimental data gives an estimate for the effective microscopic surface reflection coefficient of r≈0.87 for the oxide film precursors.

Applications of nuclear microprobes to semiconductor process developments

Nuclear microprobes have been applied to semiconductor process developments. Two or three-dimensional micro-analyses using micro-Rutherford backscattering and channeling on miniaturized structures have been demonstrated. Optimization of memory device structures using soft error mapping and ion beam induced current (IBIC) measurements has been described. Issues arising from microprobe analyses have been discussed.

Amorphous silicon/amorphous silicon carbide heterojunctionsapplied to memory device structures

It has been proposed and experimentally confirmed that band-engineered hydrogenated amorphous silicon (a-Si:H)/hydrogenated amorphous silicon carbide (a-SiC:H) heterojunctions on c-Si can be applied to electrically programmable and erasable memory devices. A test diode with the structure c-Si/graded a-SiC:H/a-Si:H/uniform a-SiC:H/Al exhibits a large hysteresis in the C-V characteristic with a retention time of 0.8 s at room temperature.

Intraventricular conduction defects: Hübener, G.: Deutsche med. Wchnschr. 64: 1222, 1938

Bipolar resistive switching memory device using Cu metallic filament in Au/Cu/Ge0.2Se0.8/W memory device structure has been investigated. This resistive memory device has the suitable threshold voltage of Vth > 0.18 V, good resistance ratio (RHigh/RLow) of 2.6 × 103, good endurance of >104 cycles with a programming current of 0.3 mA/0.8 mA, and 5 h of retention time at low compliance current of 10 nA. The low resistance state (RLow) of the memory device decreases with increasing the compliance current from 1 nA to 500 μA for different device sizes from 0.2 μm to 4 μm. The memory device can work at very low compliance current of 1 nA, which can be applicable for extremely low power-consuming memory devices.