Evaluating Resistive Memory Devices for Neuromorphic Computing Using Ultrashort Voltage Pulses

Abstract

A special purpose neural algorithm accelerator based on resistive memory could potentially reduce the energy requirements of neural algorithm implementation by six orders of magnitude over conventional general purpose GPU/CPU hardware (1). The device requirements for such a neural algorithm accelerator depend on attributes including write variability, write linearity, and read noise, as described in reference (2). Devices with multiple resistance states accessible via symmetric voltage pulses of constant magnitude are highly desired for neuromorphic hardware implementations. Tantalum oxide resistive memory devices have been previously shown to have low energy requirements and better control of conductivity during switching in the ultrashort time domain (3). We will report on how employing voltage pulses with ultrashort pulse widths allow for finer control of tantalum oxide based device conductance change per pulse (ΔG/G) unlocking additional neuromorphic states. A parameter space of pulse voltage and time is used to elucidate switching kinetics and switching energy expenditure during device operation. Lastly, the performance of several different resistive memory device structures will be comparatively evaluated for suitability in implementing a neural algorithm accelerator. This work was supported by Sandia National Laboratories’ Laboratory Directed Research and Development (LDRD) Program under the Hardware Acceleration of Adaptive Neural Algorithms Grand Challenge. Sandia National Laboratories is a multi-program laboratory managed and operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin Corporation, for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-AC04-94AL85000. REFERENCES: 1. Kadetotad, Deepak, et al. "Parallel architecture with resistive crosspoint array for dictionary learning acceleration." IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 5.2 (2015): 194-204. 2. S. Agarwal, et. al. “Resistive Memory Device Requirements for a Neural Algorithm Accelerator,” International Joint Conference on Neural Networks, (2016) 3. Strachan, John Paul, et al. “Measuring the switching dynamics and energy efficiency of tantalum oxide memristors” Nanotechnology22.50 (2011): 505402. Figure 1