Characteristics Of Memory Devices Research Articles

Delay characteristics of quasi-nonvolatile memory devices operating in positive feedback mechanism.

This study examines the memory and read delay characteristics of quasi-nonvolatile memory (QNVM) devices operating in a positive feedback mechanism through technology computer-aided design simulation. The QNVM devices exhibit a rapid operation speed of 5 ns, a significant sensing margin of approximately 8.0 μA, and a retention time of around 1 s without any external bias. These devices showcase an exceptionally brief read delay of 0.12 ns. The energy band diagrams during the memory operation are analysed to clarify the factors influencing the read delay. The write and standby conditions modulate the potential barrier height during the standby operation, thereby affecting the read delay. Moreover, the shorter rising time causes the reduction of the read delay. This study demonstrates that the QNVM device has the potential to resolve energy consumption and speed issues in nonvolatile memory devices.

Exploring the Influence of Copper Chemical Displacement Duration on Nonvolatile Oxide-based Resistive Memory Device Characteristics

Exploring the Influence of Copper Chemical Displacement Duration on Nonvolatile Oxide-based Resistive Memory Device Characteristics

Kinetic Monte Carlo simulation analysis of the conductance drift in Multilevel HfO2-based RRAM devices.

The drift characteristics of valence change memory (VCM) devices have been analyzed through both experimental analysis and 3D kinetic Monte Carlo (kMC) simulations. By simulating six distinct low-resistance states (LRS) over a 24-hour period at room temperature, we aim to assess the device temporal stability and retention. Our results demonstrate the feasibility of multi-level operation and reveal insights into the conductive filament (CF) dynamics. The cumulative distribution functions (CDFs) of read-out currents measured at different time intervals provide a comprehensive view of the device performance for the different conductance levels. These findings not only enhance the understanding of VCM device switching behaviour but also allow the development of strategies for improving retention, thereby advancing the development of reliable nonvolatile resistive switching memory technologies.

Non‐Zero and Open‐Loop Current–Voltage Characteristics in Electronic Memory Devices

AbstractThis work focuses on the non‐zero‐crossing and open‐loop current–voltage (I–V) characteristics of electronic memory devices that are studied and focused on primarily for non‐volatile memory storage applications. Gold nanoparticles‐based devices are fabricated to understand possible non‐crossing zero and open‐loop current–voltage behavior, where a non‐zero current and open loop I–V characteristics are observed at zero voltage. While other studies have attributed this behavior as a “battery effect”, this study presents an alternate perspective for non‐redox‐based charge storage memory devices. The electrical measurements clearly demonstrate that the non‐zero current and open‐loop characteristics are due to the charge trapping of the gold nanoparticles. The charge accumulation within the nanoparticle is observed to create a non‐zero potential within the device and thereby encouraging such behavior, even though the applied external voltage is zero. The longstanding mystery in deciphering if electrical measurements or the charge storage device contributes toward non‐zero property is unfurled in this article. A possible charge storage model is proposed and further verified using liquid crystals‐based two terminal devices. The presence of internal potential leads to an offset within the devices, a non‐zero current and open‐loop I–V even when the external applied voltage is zero.

Comparative analysis of low-frequency noise based resistive switching phenomenon for filamentary and interfacial RRAM devices

We investigate the low-frequency noise (LFN) characteristics of resistive switching random access memory (RRAM) devices with metal–insulator–metal structures of TiN/Ti/TiO2/TiN (filamentary) and TiN/Ti/TiO2/HfO2/TiN (interfacial). By comparing filamentary and interfacial RRAM devices, we stipulate guidelines for noise sources according to the resistance states or resistive switching mechanisms of RRAM device. In filamentary RRAM devices, the dominant noise source in the low resistance state is the localized oxygen vacancies, whereas the noise characteristics in the high resistance state represent a bulk effect. In interfacial RRAM devices, the noise characteristics in both resistance states represent the bulk effect. The physical mechanism of the multilevel cell operation is inferred by the I–V characteristics in both Icc and Vreset control modes. Specifically, the changes in the structure of the conductive filament inside the switching layer can be confirmed through LFN measurement.

Ternary Memory Behavior of Carbazole‐Based Donor–Acceptor Polymer and CdS NPs Composites

AbstractMulti‐level memory can greatly improve information density, so it has been widely studied. In this study, a carbazole‐based donor–acceptor polymer poly[2,7‐9‐(heptadecan‐9‐yl)‐9H‐carbazole‐alt‐7H‐benzimidazo[2,1‐a]benz[de]isoquinolin‐7‐one] (PCz‐BB) is synthesized, which exhibits flash‐type ternary memory behavior. Further, CdS nanoparticles (NPs) are embedded into the prepared polymer to enhance the storage performance. The current–voltage (I–V) characteristics of memory devices based on PCz‐BB:CdS composites and the effect of the embedding ratio of CdS NPs on the memory devices are studied. It is verified that the ON2/ON1/OFF current ratios of the devices at low CdS embedding concentrations are improved, and the threshold voltages are also reduced. The memory device based on the optimal embedding concentration (3 wt% CdS) exhibits a high ON2/ON1/OFF current ratio of 18631:72:1, a low threshold voltage of −0.40/−1.20 V, and excellent stability. The mechanism of resistive switching is explained by the theory of charge traps and conductive filaments. This work provides a new avenue for high‐performance multi‐level organic electrical storage materials.

Low-temperature characteristics of resistive switching memory devices based on reduced graphene oxide-phosphor composites toward reliable cryogenic electronic devices

Low-temperature electronic devices are indispensable for quantum computing and space exploration applications. However, developing memory devices that are an integral part of the control circuits of low-temperature electronic devices is highly challenging. The electrical conductivity of semiconducting materials drops at low temperatures, leading to large variations in SET/RESET voltages. A strategy for the efficient operation of nonvolatile memory devices at low temperatures should be developed. This study investigated the low-temperature resistive switching characteristics of reduced graphene oxide-phosphor composites (GPs). At cryogenic temperatures, the fabricated ITO/GP/Si3N4/p++Si device exhibited a reliable and reproducible bipolar resistive switching performance. The SET/RESET voltages of the devices remained almost constant at all temperatures ranging from 77 to 300 K. The performance of the devices was further investigated by illuminating the devices with blue laser light. The SET/RESET voltages were considerably reduced through light illumination, which is correlated to the lowering of the barrier height at the Si3N4/p++Si interface and enhanced photoconductivity in the GP film. Our studies suggest that light illumination can be a promising tool for investigating issues in ReRAM devices and improving device performance in dark conditions.

Computing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFET

In the era of artificial intelligence (AI) and the Internet of Things (IoT), the emerging data-driven applications and tasks have significantly promoted the development of national digitization. However, due to the separation of storage and computing in traditional von Neumann hardware, the resulted memory wall issue leads to heavy data transfer costs in data-intensive applications, which inhibits the improvements of energy efficiency and performance.As a novel computing paradigm deviating from the traditional architecture in the post-Moore era, the computing-in-memory (CiM) technique integrates computing logic into storage by leveraging the characteristics of memory devices and circuits to eliminate the data transfer overhead. Such a promising approach can significantly improve the energy efficiency and performance of intelligent hardware platforms. Based on the traditional CMOS and the emerging non-volatile memory device ferroelectric FET, this review summarizes the key CiM circuit designs, and discusses the integrated design and optimization approaches across the device, architecture, chip, algorithm, and application layers.

Investigation of random telegraph noise characteristics of Hf-based MONOS nonvolatile memory devices with HfO2 and HfON tunneling layers

This paper investigates the low-frequency noise (LFN) utilizing 1/f noise and random telegraph noise (RTN) characteristics of Hf-based metal/oxide/nitride/oxide/silicon (MONOS) nonvolatile memory devices with HfO2 and HfON tunneling layers (TLs). The LFN spectral density (S I D ) was investigated to evaluate the interface characteristics before and after programming/erasing cycles of 104. The devices show similar slopes of ∼1/f in all frequency regions. Although the HfON TL shows high S I D compared to the HfO2 TL, the increased ratio is 10 which is low compared to the HfO2 TL ratio of 32. As the channel length is decreased from 10 to 2 μm, the HfON TL shows a low increased ratio of S I D . Due to the nitrided characteristics, the HfON TL suppresses the degradation of the interface. Finally, it was found that the trap sites of the HfO2 TL are located near the interface by RTN measurement with the capture (τ C) and emission (τ E) time constants.

Low-Frequency 1/f Noise Characteristics of Ultra-Thin AlOx-Based Resistive Switching Memory Devices with Magneto-Resistive Responses

Low-frequency 1/f voltage noise has been employed to probe stochastic charge dynamics in AlOx-based non-volatile resistive memory devices exhibiting both resistive switching (RS) and magneto-resistive (MR) effects. A 1/fγ noise power spectral density is observed in a wide range of applied voltage biases. By analyzing the experimental data within the framework of Hooge’s empirical relation, we found that the Hooge’s parameter α and the exponent γ exhibit a distinct variation upon the resistance transition from the low resistance state (LRS) to the high resistance state (HRS), providing strong evidence that the electron trapping/de-trapping process, along with the electric field-driven oxygen vacancy migration in the AlOx barrier, plays an essential role in the charge transport dynamics of AlOx-based RS memory devices.

A scheme for enabling the ultimate speed of threshold switching in phase change memory devices

Phase change materials exhibit threshold switching (TS) that establishes electrical conduction through amorphous material followed by Joule heating leading to its crystallization (set). However, achieving picosecond TS is one of the key challenges for realizing non-volatile memory operations closer to the speed of computing. Here, we present a trajectory map for enabling picosecond TS on the basis of exhaustive experimental results of voltage-dependent transient characteristics of Ge2Sb2Te5 phase-change memory (PCM) devices. We demonstrate strikingly faster switching, revealing an extraordinarily low delay time of less than 50 ps for an over-voltage equal to twice the threshold voltage. Moreover, a constant device current during the delay time validates the electronic nature of TS. This trajectory map will be useful for designing PCM device with SRAM-like speed.

In situ learning using intrinsic memristor variability via Markov chain Monte Carlo sampling

Resistive memory technologies could be used to create intelligent systems that learn locally at the edge. However, current approaches typically use learning algorithms that cannot be reconciled with the intrinsic non-idealities of resistive memory, particularly cycle-to-cycle variability. Here, we report a machine learning scheme that exploits memristor variability to implement Markov chain Monte Carlo sampling in a fabricated array of 16,384 devices configured as a Bayesian machine learning model. We apply the approach experimentally to carry out malignant tissue recognition and heart arrhythmia detection tasks, and, using a calibrated simulator, address the cartpole reinforcement learning task. Our approach demonstrates robustness to device degradation at ten million endurance cycles, and, based on circuit and system-level simulations, the total energy required to train the models is estimated to be on the order of microjoules, which is notably lower than in complementary metal–oxide–semiconductor (CMOS)-based approaches. The non-ideal characteristics of resistive memory devices can be used to develop low-power and resilient probabilistic neuromorphic computing hardware, suitable for highly constrained edge-based applications.

Spray-Coated, Volatile and Nonvolatile, Two-Terminal, Resistive Switching Memory Devices Comprising Liquid-Exfoliated Black Phosphorus and Graphene Layers

Resistive switching memory devices fabricated with black phosphorus inks showed volatile memory device characteristics, specifically static random access memory (SRAM) and bipolar resistive switching. A high ON-/OFF-current ratio of 6.5 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> was obtained at a reading voltage of 0.5 V with good retention stability (over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> s). Multilevel data storage performance under different compliance currents was demonstrated. Importantly, a nonvolatile memory device was also fabricated, using an ink that comprised thinner, on average, black phosphorus flakes with a narrower thickness distribution than the ink used in the above described devices. The nonvolatile memory device showed good write/erase operation, like flash memory, during 100 endurance cycles, and good retention stability with 1.9 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> of on/off ratio at 0.5 V. According to these results, we suggest that thin films of liquid-exfoliated black phosphorus deposited by spray coating are suitable for low-cost, solution-processed, two-terminal resistive memory devices, either volatile or nonvolatile ones, the memory device type being controlled by the details of the ink preparation process, and the resulting flake thickness distributions.

Comparative studies on vertical-channel charge-trap memory thin-film transistors using In-Ga-Zn-O active channels deposited by sputtering and atomic layer depositions

Vertical-channel charge-trap memory thin film-transistors (V-CTM TFTs) using oxide semiconductors were fabricated and characterized, in which In-Ga-Zn-O (IGZO) channels were prepared by sputtering and atomic-layer deposition (ALD) methods to elucidate the effects of deposition process. The vertical-channel gate stack of the fabricated device was verified to be well implemented on the vertical sidewall of the spacer patterns due to excellent step-coverage and self-limiting mechanisms of ALD process. The V-CTM TFTs using ALD-IGZO channel exhibited a wide memory window (MW) of 15.0 V at a VGS sweep of ±20 V and a large memory margin of 1.6 × 102 at a program pulse duration as short as 5 ms. The programmed memory margin higher than 105 did not experience any degradation with time evolution for 104 s. The mechanical durability was also evaluated after the delamination process of polyimide (PI) film. There were no marked variations in charge-trap-assisted MW even at a curvature radius of 1 mm and programmed memory margin even after repeated program operations of 104 cycles. The introduction of ALD process for the formation of IGZO active channel was suggested as a main process parameter to ensure the excellent memory device characteristics of the V-CTM TFTs.

Dependence of InGaZnO and SnO2 thin film stacking sequence for the resistive switching characteristics of conductive bridge memory devices

We have investigated the switching mechanism of conductive bridge random access memory (CBRAM) with Ag/SnO2/Pt, Ag/InGaZnO(IGZO)/Pt and their hybrid oxide devices with different stacking sequence (Ag/SnO2/IGZO/Pt and Ag/IGZO/SnO2/Pt). Typical bipolar resistive switching is observed in single layered devices and an Ag/SnO2/IGZO/Pt hybrid device. Interestingly, a stable and reproducible unipolar resistive switching is observed for a hybrid device with a stacking sequence of Ag/IGZO/SnO2/Pt. This result suggests that the staking sequence of dielectrics in the IGZO and SnO2 electrolyte determines unipolar or bipolar switching. The different switching types in the hybrid electrolyte are based on different migration or diffusion rates of Ag ions in the solid electrolyte and redox reaction rates at the electrodes. And as compared to single layered devices, the hybrid structured devices exhibit low operation voltages, higher ION/IOFF ratio, uniform switching cycles and better endurance and retention characteristics. The results and switching mechanisms demonstrated here in hybrid devices can be extended to other hybrid devices based on CBRAM device.

Protein Nanosphere Anchors for Stabilizing Hydroxylated Polymer Chains in Organic Memory Transistors with Outstanding Retention Characteristics

AbstractIt is demonstrated that a heme protein (cytochrome c [Cyt c]) nanosphere plays a strong anchoring role in binding hydroxyl groups of poly(vinyl alcohol) (PVA) leading to outstanding high‐temperature (100 °C) retention characteristics of transistor‐type organic memory devices (TOMDs). The PVA:Cyt c layers are spin‐coated on indium tin oxide gate electrodes from aqueous solutions with various Cyt c contents up to 50 wt%, followed by the formation of poly(3‐hexylthiophene) (P3HT) channel layers and nickel/aluminum top source/drain electrodes in TOMDs. Results show that adding 20 wt% Cyt c improves the drain current of devices in the presence of good hysteresis characteristics, which are maintained even after exposure to high‐temperature conditions (100 °C). The excellent conservation of hysteresis characteristics is attributed to the formation of Cyt c nanospheres that act as an anchoring point to retard the relaxation of PVA chains via specific interactions (hydrogen bonding etc.) between amino groups in the Cyt c nanosphere surfaces and hydroxyl groups in the PVA chains. The optimized PVA:Cyt c layers (20 wt% Cyt c, thermal treatment at 100 °C) deliver excellent retention characteristics to TOMDs, whereas no memory function is measured in the case of the pristine PVA layers at 100 °C.

Design strategies for improvement in nonvolatile memory characteristics of metal-ferroelectric-metal-insulator-semiconductor capacitors using ferroelectric Hf0.5Zr0.5O2 thin films

The effects of top electrode and thickness control of ferroelectric HfxZr1−xO2 (HZO) film on the memory device characteristics were investigated for metal-ferroelectric-metal-insulator-semiconductor (MFMIS) capacitors. It was suggested from capacitance-voltage analysis for the MFM and MFMIS capacitors that the Al top electrode increased leakage current components and caused memory retention degradation owing to the formation of intermediate transistion layer at interfaces with HZO. Alternatively, the choice of Pt top electrode was appropriate to guarantee sound device operations without any reaction at interfaces. When the HZO thickness increased from 20 to 30 nm, the maximum memory window supported by ferroelectric field-effect increased from 2.6 to 3.1 V at an area ratio (MIS:MFM) of 60. Load-line and operating-point analysis show that polarization loops close to more saturated polarizations can be exploited for the memory operations of MFMIS capacitors using thicker HZO films. As a result, for the MFMIS capactior using 30 nm-thick HZO, the capacitance loss at on-state was only 8.7% after a lapse of retention time for 104 s. Choice of top electrode and control of HZO thickness were found to be important design parameters for highly-functional ferroelectric transistors using MFMIS gate-stack structures.

Effects of Grain Size on the Electrical Characteristics of Three-Dimensional NAND Flash Memory Devices.

Polysilicon is commonly used as the channel in three-dimensional (3D) NAND flash memory devices. However, degradation of device performance due to grain boundary traps in the channel is a major issue. The saturation on-current level, threshold voltage (Vth), and electron density of 3D NAND flash memory devices with randomly generated grain boundaries were investigated by using three-dimensional technology computer-aided design (TCAD) simulation. The device performance tended to degrade with an increasing number of grains, and the direction of the grains significantly affected the device performance. The large decrease in the electron density of the channel region due to the direction of the grains can be explained according to the formation of the depletion region.

Threshold switching dynamics of pseudo-binary GeTe–Sb2Te3 phase change memory devices

Phase change materials have gained significant interest for the development of high-speed non-volatile electronic memory; however the dependence of electrical switching properties on the material composition for improved device performance is poorly understood. Here, we report an exhaustive experimental analysis on electrical conduction in sub-threshold regime and threshold switching characteristics of Ge1Sb2Te4, Ge2Sb2Te5 and Ge8Sb2Te11 phase change memory (PCM) devices. Thereby, a correlation between material composition and the relevant change in device properties is described. The study of sub-threshold conduction in these devices reveals that the electrical conductivity in the amorphous state decreases upon increasing GeTe content in the (GeTe)x–(Sb2Te3)1−x tie-line leading to better stability of the amorphous state. Moreover, the threshold switching characteristics of these materials demonstrate that upon reducing the GeTe content in (GeTe)x–(Sb2Te3)1−x tie-line, the threshold voltage is reduced and thereby, low power switching of PCM device is achieved. These experimental findings therefore, allow the choice of material composition that enables the interplay between threshold switching characteristics and crystallization speed of active material in the GeSbTe family to tailor the property portfolio suitable for the development of low power, high-speed, non-volatile PCM devices for future computing.

Characterization on the operation stability of mechanically flexible memory thin-film transistors using engineered ZnO charge-trap layers

The charge-trap memory thin-film transistors (CTM-TFTs) using ZnO charge-trap layer (CTL) were fabricated and characterized, in which ZnO CTL was deposited by atomic layer deposition (ALD) and the deposition temperatures were controlled to be 75, 100, and 125 °C to improve both specifications of device characteristics and stability for the flexible memory devices. The CTM-TFT using ZnO CTL deposited at 100 °C obtained a wide memory window (MW) of 14.7 V, large memory margin between ON- and OFF-states (ION/IOFF, 7.3 × 106) at 1 µs voltage pulses. The ION/IOFF larger than 107 was also obtained with a progress of retention time. It was noteworthy that the deposition temperature for the ZnO CTL was worked as one of the most important control parameters affecting the memory device characteristics of the fabricated flexible CTM-TFTs. Alternatively, the fast program operation and long retention time were suggested to result from a suitable number of trap sites and their appropriate positions within the ZnO CTL prepared at 100 °C. The improved device stabilities were guaranteed even under bending condition at a radius of curvature of 10 mm after the delamination process of PI film substrate from carrier glass.