Computing-in-memory circuits and cross-layer integrated design and optimization: from SRAM to FeFET

Abstract

In the era of artificial intelligence (AI) and the Internet of Things (IoT), the emerging data-driven applications and tasks have significantly promoted the development of national digitization. However, due to the separation of storage and computing in traditional von Neumann hardware, the resulted memory wall issue leads to heavy data transfer costs in data-intensive applications, which inhibits the improvements of energy efficiency and performance.As a novel computing paradigm deviating from the traditional architecture in the post-Moore era, the computing-in-memory (CiM) technique integrates computing logic into storage by leveraging the characteristics of memory devices and circuits to eliminate the data transfer overhead. Such a promising approach can significantly improve the energy efficiency and performance of intelligent hardware platforms. Based on the traditional CMOS and the emerging non-volatile memory device ferroelectric FET, this review summarizes the key CiM circuit designs, and discusses the integrated design and optimization approaches across the device, architecture, chip, algorithm, and application layers.