Memory Bus Research Articles

Revolutionising Ai Deployment: Survey On Hardware Acceleration for Machine Learning Optimisation and Resilience

This compilation of research studies holds the utmost significance in hardware acceleration for machine learning. In our current era, characterised by the exponential growth of artificial intelligence (AI) applications, these studies tackle crucial challenges in optimising neural network accelerators' performance, energy efficiency, and resilience. The importance lies in their potential to revolutionise AI implementation across various domains. Efficient hardware accelerators are a cornerstone in unlocking the full potential of AI, enabling breakthroughs in deep learning, high-speed train fault detection and isolation, and numerous other applications. By improving memory management, facts placement, bus scheduling, and fault tolerance, that research paves the way for AI structures which are both powerful and sustainable, making AI accessible and impactful in a wide variety of fields. This research is important for fostering the growth and adoption of AI, ultimately remodelling how we interact with technology and facts in our daily lives.

High energy efficient and configurable CIM macro for image processing

Traditional von Neumann architecture, characterized by separate memory and processing units connected by a limited-capacity memory bus, faces challenges in handling tasks with high energy efficiency requirements. In contrast, the compute-in-memory (CIM) architecture offers a promising alternative, facilitating high parallelism in data processing while integrating storage functions, thereby significantly reducing memory access frequency and power consumption. This study presents a fully digital CIM macro featuring a novel self-write-back 12T cell. This bitcell is capable of performing Boolean logic operations and autonomously writing back results into the in-situ cell, thereby significantly improving energy efficiency.This can be used for binary logical operations between each pixel of two images without requiring additional storage area. A bidirectional read/write architectural design enables matrix transposition. This can achieve image rotation.Additionally, this novel 12T cell also offers the option to choose not to write back the results of logical operations, thereby providing the flexibility and configurability for image processing. Combined with an adder tree, it enables multiply-and-accumulate (MAC) operation for convolutional neural networks(CNNs). This can be used for feature extraction. We propose an 18T full adder structure with lower power-delay product than current state-of-the-art full adders, which is advantageous for improving the synthesis performance of the adder tree.The CIM macro supports a 4-bit × 4-bit MAC operation. The proposed CIM macro, designed and simulated using a 28 nm CMOS process with a 16 Kb static random access memory (SRAM), demonstrates promising results. At VDD = 0.9 V, the logic operation energy consumption is 1.35 fJ/bit with an energy efficiency of 740TOPS/W, and MAC operation energy consumption is 15.91 fJ/bit with an energy efficiency of 62.85 TOPS/W.

A design strategy for analyzing signal integrity in DDR3 bus of high speed embedded systems

A complex modern embedded system using a multi-core Central Processing Unit (CPU) toward a compact integrated design in a single Printed Circuit Board (PCB). One of the biggest challenges of the design is to meet the Signal Integrity for high speed Double Data Rate 3 Synchronous Dynamic Random-Access Memory (DDR3) bus. A typical strategy to solve the challenge is the simulation on the computer, but this is not always an effective solution as has a gap between simulation software and practical PCB. The gap is correlated to localized changes in copper density within the PCB and characterization of heterogeneous materials in PCB that could lead to differences in the real PCB. The purpose of the research presents an analysis methodology to design DDR) memory interfaces in high speed embedded systems, related to Signal Integrity and the impact of copper density on PCB trace impedances to overcome these challenges. Moreover, the presented design methodology is also applied to the next generation DDR as well as other styles of CPU.

Caiti: I/O transit caching for persistent memory-based block device

Byte-addressable non-volatile memory (NVM) sitting on the memory bus is employed to make persistent memory (pmem) in general-purpose computing systems and embedded systems for data storage. Researchers develop software drivers such as the block translation table (BTT) to build block devices on pmem, so programmers can keep using mature and reliable conventional storage stack while expecting high performance by exploiting fast pmem. However, our quantitative study shows that BTT underutilizes pmem and yields inferior performance, due to the absence of the imperative in-device cache. We add a conventional I/O staging cache made of DRAM space to BTT. As DRAM and pmem have comparable access latency, I/O staging cache is likely to be fully filled over time. Continual cache evictions and fsyncs thus cause on-demand flushes with severe stalls, such that the I/O staging cache is concretely unappealing for pmem-based block devices. We accordingly propose an algorithm named Caiti with novel I/O transit caching. Caiti eagerly evicts buffered data to pmem through CPU’s multi-cores. It also conditionally bypasses a full cache and directly writes data into pmem to further alleviate I/O stalls. Experiments confirm that Caiti significantly boosts the performance with BTT by up to 3.6×, without loss of block-level write atomicity.

APPLICATION OF TEMPERATURE DEPENDANCES OF PARAMETERS IN A SINGLE-DIODE FIVE-PARAMETER MODEL OF SOLAR PANELS

Memory built-in self-test (MBIST) continues to have its unique place in IC industry. It provides test and repair capabilities which significantly increase IC manufacturing yield. In general, the integration of MBIST solutions in a system on chip (SoC) is done via automated flows. Possible issues occurring in the flow should not be skipped as it will degrade the performance of SoC or even may disrupt its functioning. The probability of issues is increased if the SoC has specific structure adding limitations for MBIST solution such as testing the memories by shared interface. Dedicated validation environments (VE) help to overcome these issues. Validation challenges of the MBIST solution via a shared interface for a specific case of multi memory bus BIST engines (MMBBE) are discussed, and a solution is proposed. To avoid the exhaustion increase for the integration scenarios random choices combined with some exhaustions are done depending on a given feature’s priority. Meantime, it is mentioned that for big configurations the usage of random values of parameters might bring to missing some corner cases. Due to that it is recommended to use further some learning methods for reducing the VE iterations and exhaustion within a given iteration. In all the cases, a targeted analysis should be done and decisions should be additionally taken to find out a reasonable number of these iterations. In this paper, a methodology is proposed to soften the mentioned above exhausti-on. A new algorithm of learning is proposed, and the results of the algorithm application are adduced which justify its efficiency in reducing the exhaustion.

Design and Optimization of a Distributed File System Based on RDMA

With the rapid development of computer and network technology, to deal with explosively growing mass data correctly, distributed file systems have come into being, and they have been applied in many enterprises. However, in the packet storage process, the traditional TCP/IP transmission protocol has to pass through the operating system and application software layer. It takes up many server resources and memory bus bandwidth, which places a heavy burden on the server’s CPU and memory. In this paper, we analyze the research status of the distributed file system based on analyzing and comparing the advantages of RDMA over traditional TCP Ethernet communication architecture. We propose an optimization scheme for the network transmission performance of the original FastDFS to replace the original TCP module with an RDMA network communication module, and we design a lightweight distributed file system with higher performance than the original FastDFS, which is suitable for small file storage. Using the zero-copy technology and kernel bypass technology of soft RDMA, the network communication mechanism in FastDFS is optimized to free the server’s CPU from heavy data processing work. In this paper, the RDMA-based FastDFS is compared with the original FastDFS. The test results show that the network transmission performance of the optimized FastDFS is improved compared with the original FastDFS, which achieves the expected effect and can better meet the requirements of mass small file storage for today’s Internet applications.

Polling-Based Memory Interface

Non-volatile memory has been extensively researched as the alternative for a DRAM-based system; however, the traditional memory controller cannot efficiently track and schedule operations for all the memory devices in heterogeneous systems due to different timing requirements and complex architecture supports of various memory technologies. To address this issue, we propose a hybrid memory architecture framework called POMI (POlling-based Memory Interface). It uses a small buffer chip inserted on each DIMM (Dual In-line Memory Module) to decouple operation scheduling from the controller to enable the support for diverse memory technologies in the system. Unlike the conventional DRAM-based system, POMI uses a polling-based memory bus protocol for communication and to resolve any bus conflicts between memory modules. The buffer chip on each DIMM will provide feedback information to the main memory controller so that the polling overhead is trivial. We propose two unique designs. The first one adds additional bus lines for sending the feedback information, and the second one utilizes the Command/Address bus. The framework provides several benefits: a technology-independent memory system, higher parallelism, and better scalability. Our experimental results show that POMI can efficiently support both homogeneous and heterogeneous systems. Compared with the conventional DDR4-2400 implementation, our scheme improves the performance of memory-intensive workloads by 3.7% on average. Compared with an existing interface for hybrid memory systems, Twin-Load, it also improves performance by 22.0% on average for memory-intensive workloads.

Energy-efficient In-Memory Address Calculation

Computation-in-Memory (CIM) is an emerging computing paradigm to address memory bottleneck challenges in computer architecture. A CIM unit cannot fully replace a general-purpose processor. Still, it significantly reduces the amount of data transfer between a traditional memory unit and the processor by enriching the transferred information. Data transactions between processor and memory consist of memory access addresses and values. While the main focus in the field of in-memory computing is to apply computations on the content of the memory (values), the importance of CPU-CIM address transactions and calculations for generating the sequence of access addresses for data-dominated applications is generally overlooked. However, the amount of information transactions used for “address” can easily be even more than half of the total transferred bits in many applications. In this article, we propose a circuit to perform the in-memory Address Calculation Accelerator. Our simulation results showed that calculating address sequences inside the memory (instead of the CPU) can significantly reduce the CPU-CIM address transactions and therefore contribute to considerable energy saving, latency, and bus traffic. For a chosen application of guided image filtering, in-memory address calculation results in almost two orders of magnitude reduction in address transactions over the memory bus.

Schedulability analysis for 3-phase tasks with partitioned fixed-priority scheduling

Multicore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared memory bus that connects the cores to the off-chip main memory. This sharing of memory bus may cause tasks running on different cores to compete for access to the main memory whenever data/instructions are need to be read/written from/to the main memory. Such competition is problematic, as it may cause variations in the execution time of tasks in a non-deterministic way. To reduce the complexity of analyzing this problem, the 3-phase task model was proposed that divides tasks’ executions into distinct memory and execution phases. The distinctive memory phases are then scheduled to eliminate/minimize main memory contention between concurrently executing tasks. However, 3-phase tasks running on different cores may still compete to access the shared memory bus/main memory in order to execute memory phases. This paper presents a partitioned scheduling-based approach that allows one to derive memory bus contention-aware worst-case response time of tasks that follow the 3-phase task model. In particular, the bus-contention analysis is derived by considering two memory access models, i.e., (i) dedicated memory access model, where a core having allowed to access the main memory via memory bus is permitted to execute more than one memory phase, and (ii) fair memory access model, that restrict each core to execute only one memory phase in its allocated bus access. Both these models represent different system and application requirements, and the resulting bus contention of tasks may vary depending on the considered model. To evaluate the effectiveness of the proposed bus contention analysis, we compare its performance against an existing analysis in the state-of-the-art by performing (i) case-study experiments, using benchmarks from the Mälardalen Benchmark suite, and (ii) empirical evaluation using synthetic task sets. Results show that our proposed analysis can improve task set schedulability of 3-phase tasks by up to 88 percentage points.

The past, present and future of indexing on persistent memory

Persistent memory (PM) based indexing techniques have been proposed to build fast yet persistent indexes that sit on the memory bus. Over the past decade, numerous techniques have been proposed with various assumptions and different properties (e.g., some of them were proposed before real PM became available), making it hard for researchers and practitioners to gain a comprehensive understanding of the area. In this tutorial, we give a comprehensive overview of PM indexing techniques, covering both range and hash indexes. We contrast the designs proposed before and after real PM became available, summarize the common and useful design techniques, and discuss potential future challenges and opportunities in this area.

Evaluating persistent memory range indexes

Scalable persistent memory (PM) has opened up new opportunities for building indexes that operate and persist data directly on the memory bus, potentially enabling instant recovery, low latency and high throughput. When real PM hardware (Intel Optane Persistent Memory) first became available, previous work evaluated PM indexes proposed in the pre-Optane era. Since then, newer indexes based on real PM have appeared, but it is unclear how they compare to each other and to previous proposals, and what further challenges remain. This paper addresses these issues by analyzing and experimentally evaluating state-of-the-art PM range indexes built for real PM. We find that newer designs inherited past techniques with new improvements, but do not necessarily outperform pre-Optane era proposals. Moreover, PM indexes are often very competitive with or even outperform indexes tailored for DRAM, highlighting the potential of using a unified design for both PM and DRAM. Functionality-wise, these indexes still lack good support for variable-length keys and handling NUMA effect. Based on our findings, we distill new design principles and highlight future directions.

Design and Simulation of Content-Aware Hybrid DRAM-PCM Memory System

Phase Change Memory (PCM) can directly connect persistent memory to main memory bus, while it achieves high read throughput and low standby power, the critical concerns are its poor write performance and limited durability. A naturally in-spired design is the hybrid memory architecture that fuses DRAM and PCM, so as to exploit the positive aspects of both types of memory. Unfortunately, existing solutions are seriously challenged by the limited main memory size, which is the primary bottleneck of in-memory computing. In this paper, we introduce a novel Content Aware Hybrid DRAM-PCM memory system framework—CAHRAM, which exploits deduplication to improve line sharing with high memory efficiency. It reduces write traffic to hybrid memory by removing unnecessary duplicate line writes, thereby further enhancing the write endurance of PCM. And it also substantially extends available free memory space by coalescing redundant lines in hybrid memory. We also design a reference-based page migration technique to minimize the access overheads caused by the performance gap between DRAM and PCM. Compared with the state-of-the-art in a hybrid memory simulator, our experiment results show that CAHRAM can achieve the highest I/O performance and the longest PCM lifetime with the competitive efficiencies in space and energy.

OpenMDS: An Open-Source Shell Generation Framework for High-Performance Design on Xilinx Multi-Die FPGAs

FPGA is a promising platform in designing hardware due to its design flexibility and fast development cycle, despite the device's limited hardware resources. To address this, latest FPGAs have adopted a multi-die architecture that employs multiple dies in a single device to provide abundant hardware resources. However, the multi-die architecture causes critical timing issues when signal paths cross the die-to-die boundaries, adding another design challenge in using FPGA. We propose OpenMDS, an open-source shell generation framework for high-performance design on Xilinx multi-die FPGAs. Based on the user's design requirements, it generates an optimized shell for the target FPGA via die-level kernel encapsulation, automated bus pipelining, and customized floorplanning. To evaluate our shell generation, we compare its implementation results against Xilinx's Vitis framework. As a result, OpenMDS uses average 20% less logic resources than Vitis for the same shell functionality. To show its practicality, we use OpenMDS for the design of machine learning accelerator that contains multiple systolic-array processors. OpenMDS achieves 247MHz and 235MHz kernel frequency and 400MHz and 429MHz memory bus frequency for U50 and U280, respectively, for the accelerator design over 90% logic utilization, claiming up to 12.27% and 22.92% higher kernel and memory bus frequency over Vitis.

Technology Strategy for Meticulous Governance of Smart Cities: Memory Bus Width Aware Pruning for Efficient Image Super-Resolution Implementation in FPGA

The mega-city governance is based on the aggregation, collation, development and application of multi-scene data, and efficient access to scene data is a key link to promote the meticulous governance of smart cities. Super-resolution technique is the process of upscaling and improving the details within an image. In this paper, we implement a 16-layer residual neural network (ResNet) for the efficient image super-resolution in FPGA. We discover that the memory access is the major performance bottleneck of this implementation. To reduce the memory access overhead, we design a pruning algorithm with the consideration of the memory bus width. Since the memory used in our design generates 256 bits for each access, the proposed pruning algorithm drops the kernel by aligning this bit width. That is, all kernels in one layer are ranked by its L1-norm and we drop the kernels out of the 256 bits. The experimental results show that the proposed method reduces the number of weights by 50% compared with the baseline. As a result, the inference speed can be enhanced by 3 times.

Interference-Aware Schedulability Analysis and Task Allocation for Multicore Hard Real-Time Systems

There has been a trend towards using multicore platforms for real-time embedded systems due to their high computing performance. In the scheduling of a multicore hard real-time system, there are interference delays due to contention of shared hardware resources. The main sources of interference are memory, cache memory, and the shared memory bus. These interferences are a great source of unpredictability and they are not always taken into account. Recent papers have proposed task models and schedulability algorithms to account for this interference delay. The aim of this paper is to provide a schedulability analysis for a task model that incorporates interference delay, for both fixed and dynamic priorities. We assume an implicit deadline task model. We rely on a task model where this interference is integrated in a general way, without depending on a specific type of hardware resource. There are similar approaches, but they consider fixed priorities. An allocation algorithm to minimise this interference (Imin) is also proposed and compared with existing allocators. The results show how Imin has the best rates in terms of percentages of schedulability and increased utilisation. In addition, Imin presents good results in terms of solution times.

Effective and Secure vWSN Applications in a Virtualized Cloud Computing Environment

Security is one of the key concerns in cloud computing. We are proposing Virtual Wireless Sensor Network (vWSN) which is one of the key features of cloud computing in the area of agriculture. Our main focuses are effective and secure vWSN in virtualized cloud computing environment with enhanced security to detect environmental monitoring, humidity monitoring, soil moisture, air quality (pollution) monitoring, insect monitoring, pest and disease control, which is based on virtualization and cloud computing technology, centrally managed device having flexible and configurable parameter with less maintenance and operational cost. To the best of our knowledge, vWSN is the first approach to agriculture based on extensional WSN information. WSN contains both control plane (signaling) and data plane (forwarding) coupled together.WSN is a specific purpose computer containing hardware whose main components are memory, CPU, IO, registers, Data and address bus, timer, sensor, computing logic and decision making logic. WSN is a physical device which needs to be placed in the field in certain topology (Ring, mesh, tree, star) which may need to be protected for damage and erosion due to various parameter including but not limited to physical theft, damage due to weather, animal and various other reason. In this paper our approach is to propose virtualized model to replace physical wireless sensor network (WSN) to virtual machine (VM) based vWSN which can be deployed on the cloud. Since security is one of the major concern for VM in cloud computing therefore we also proposed the enhanced 3-tier security model for vWSN.

On- and Off-chip Signaling and Synchronization Methods in Electrical Interconnects

Advances in integrated circuit (IC) fabrication technology, coupled with aggressive circuit design, have led to an exponential growth in speed and integration levels. However, to improve overall system performance, the communication speed between on-chip subsystems and between ICs in printed circuit board must increase accordingly. Currently, communication bus links in various applications approach Gbps (gigabits per second) data rates. These applications include high-speed network switching, local area network, memory buses, and multiprocessor interconnection networks. In this article, we analyze the most common (popular) CMOS implementations of high speed on- and off-chip links (electrical interconnects) and show that the links’ performance should continue to scale with technology. In addition, we point to the fact that global electrical interconnects are widely acknowledged as a limiting factor in future on-chip and off-chip designs. Novel electrical interconnect driving techniques like multi-level multi-wire signaling, and GALS synchronization method primarily intended to improve performance of on-chip electrical interconnects, has been shortly analyzed. In the future, in order to handle the electrical interconnects’ finite bandwidth (data rate higher than 100 Gbps), however, more sophisticated signaling and synchronization methods will be required.

Bus-contention aware WCRT analysis for the 3-phase task model considering a work-conserving bus arbitration scheme

Nowadays multicore processors are used in most modern systems. However, their applicability in systems with stringent timing requirements is still ongoing research. The main reason behind this is the difficulty of ensuring the timing correctness of tasks executing on such systems as they comprise a number of shared hardware resources, as for instance, caches, memory bus, and the main memory. Concurrent accesses to any of these shared resources can generate uncontrolled interference, which complicates the estimations of the worst-case execution time and the worst-case response time of tasks. The use of the 3-phase task execution model helps in upper bounding the contention due to the sharing of bus/main memory in multicore systems. This model divides the execution time of tasks into distinct memory and execution phases, where tasks can only access the bus/main memory during their memory phases. This makes bus and memory access patterns of tasks predictable by enabling a precise computation of bus/memory contention. In this work, we show how the bus contention can be computed for the 3-phase task model considering a round-robin-based arbitration policy at the memory bus. We differ from existing works that analyze the time-division multiple access and first-come-first-serve-based bus arbitration policies. First, we present a solution that models the bus contention that can be suffered/caused by tasks executing on the same/remote cores of a multicore system under an RR-based bus arbitration scheme. Then, the impact of the resulting bus contention on taskset schedulability is evaluated. Experimental results show that our proposed RR-based bus contention analysis can improve taskset schedulability by up to 100 percentage points when compared to a state-of-the-art TDMA-based analysis, and up to 40 percentage points when compared to the state-of-the-art FCFS-based bus contention analysis.

A Survey of Techniques for Reducing Interference in Real-Time Applications on Multicore Platforms

This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.

APEX

The recently released persistent memory (PM) offers high performance, persistence, and is cheaper than DRAM. This opens up new possibilities for indexes that operate and persist data directly on the memory bus. Recent learned indexes exploit data distribution and have shown great potential for some workloads. However, none support persistence or instant recovery, and existing PM-based indexes typically evolve B+-trees without considering learned indexes. This paper proposes APEX, a new PM-optimized learned index that offers high performance, persistence, concurrency, and instant recovery. APEX is based on ALEX, a state-of-the-art updatable learned index, to combine and adapt the best of past PM optimizations and learned indexes, allowing it to reduce PM accesses while still exploiting machine learning. Our evaluation on Intel DCPMM shows that APEX can perform up to ~15× better than existing PM indexes and can recover from failures in ~42ms.