Abstract
This survey reviews the scientific literature on techniques for reducing interference in real-time multicore systems, focusing on the approaches proposed between 2015 and 2020. It also presents proposals that use interference reduction techniques without considering the predictability issue. The survey highlights interference sources and categorizes proposals from the perspective of the shared resource. It covers techniques for reducing contentions in main memory, cache memory, a memory bus, and the integration of interference effects into schedulability analysis. Every section contains an overview of each proposal and an assessment of its advantages and disadvantages.
Highlights
In a real-time system, the application’s response time to external stimuli must be within a specified time interval
Description Memory bandwidth allocation Prioritize soft real-time applications Focuses on partitioned scheduling Budget-based memory bandwidth regulation Dynamic memory bandwidth allocation Re-design of memory controllers New memory controller architecture Memory Inter-Arrival Time Traffic Shaping Bandwidth Regulation Unit (BRU) Execution model composed of rules Scheduling table Predictable Execution Model Acquisition Execution Restitution Execution profile and resource allocation Arbitration policy Time Division Multiple Access (TDMA) arbitration policy Time Division Multiplexing (TDM) Multi-TDMA model Memory bandwidth reservation mechanism Persistence-aware bus contention analysis Bounding the worst-case bus contention
Multicore processors show an increasing usage trend due to improvements in performance and efficiency compared to integrated systems with a single-core CPU and the possibility of running composite mixed-criticality application workloads
Summary
In a real-time system, the application’s response time to external stimuli must be within a specified time interval. The use restrictions of each of the available resources can determine the response time of a running task This analysis requires obtaining the Worst-Case Execution Time (WCET) as accurately as possible [1], [2]. Users who design and implement real-time systems on multicore platforms need to identify the main sources of interference and the techniques to obtain more deterministic runtime behavior. This survey provides an overview of the scientific literature on reducing interference in real-time applications on multicore platforms. But significant, were the proposals for interference reduction techniques in the shared main memory and the shared memory bus, representing 16 percent and 24 percent, respectively
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
