Measured Rms Jitter Research Articles

An evenly-spaced-phase all-digital DLL using dual-loop SAR control

This study introduces an all-digital delay-locked loop (ADDLL), which generates 20 evenly-spaced-phase clock signals. A successive-approximation register (SAR)-based dual-loop control is used to realize the locking process of the ADDLL. A modified SAR unit combined with a tri-state digital phase detector (TSDPD) is adopted to achieve a closed-loop operation of the ADDLL. A delay matrix, which can significantly reduce the jitter accumulation, is used to generate evenly spaced phases without using a long-cascaded delay line. Additional harmonic-lock detector circuits are added to the two control loops to avoid the harmonic lock issue. The ADDLL is designed and fabricated using a 0.18μm mixed-signal CMOS technology with an active area of 0.109 μm2. The lock range of the ADDLL is 30–230 MHz and the power consumption of the ADDLL is 8.9 mW at 100 MHz. The measured rms jitter is 23.3 ps at 100 MHz, and the results show a good linearity of the multiphase outputs at a 100 MHz input clock where the maximum DNL and INL are 0.08 and -0.22 LSB, respectively. The proposed ADDDLL is highly suitable for low-frequency, low-power, and high-time-resolution applications.

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner

This work presents a low-jitter and low out-of-band noise two-core fractional- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$N$ </tex-math></inline-formula> digital bang-bang phase-locked loop (PLL). Two novel techniques are introduced to efficiently suppress the quantization noise (QN) of the digitally controlled oscillator (DCO) and to achieve an optimal trade between power consumption and PLL noise. The digital period averaging technique, working in background of the main system, enables the use of a low-power XOR-based quadrupler for clocking <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> modulator dithering the DCO tuning word. The true-in-phase combiner circuit implements a digitally assisted power combination of two PLL outputs, to optimally reduce the impact of the PLL noise sources. The prototype, implemented in a standard 28-nm CMOS process, has a core area of 0.47 mm2 and synthesizes frequencies from 8.5 to 10.5 GHz while dissipating 36 mW. The measured rms jitter (integrated from 1 kHz to 100 MHz and including spurs) is 72 fs for near-integer channels, with a worst case fractional spur of −59.7 dBc, while the measured out-of-band noise is −140.7 dBc/Hz at a 10-MHz offset.

A 1.6-GHz DPLL Using Feedforward Phase-Error Cancellation

A digital phase-locked loop (DPLL) using the feedforward phase-error cancellation (FPC) is presented. The phase error of this DPLL using a digitally controlled ring oscillator is quickly canceled by a digitally controlled delay line (DCDL), which improves the phase noise performance. The loop gain of this FPC DPLL is also calibrated. In addition, a dead-zone-free (DZF) bang-bang phase-frequency detector (BBPFD) is presented to enhance the resolution of the time-to-digital converter (TDC). This proposed DPLL is fabricated in a 40-nm CMOS process which occupies 0.05 mm2. The measured rms jitter integrated from 1 kHz to 100 MHz is 788 fs at 1.6 GHz. The measured reference spur is −57.84 dBc for a 50 MHz reference frequency. Its power consumption is 5 mW for a 1.1-V supply voltage.

A 14 Gbps VCSEL driving ASIC in 55 nm for NICA multi purpose detector project

This paper presents the design and the test results of a 14 Gbps VCSEL driving ASIC with a novel output driver structure fabricated in a 55 nm CMOS process. It consists of an equalizer stage, a limiting amplifier stage and an output driver stage. The equalizer stage uses the CTLE structure to compensate the high frequency losses at the PCB traces, bonding wires and input pads. To meet both the gain/bandwidth requirements and the area restriction, the limiting amplifier stage adopts the inductor-shared peaking technology. To increase the voltage headroom of the output driver stage and improve the bandwidth, a novel output driver structure using the on-chip AC coupling, the stacked current source and the double feedforward compensation technique is proposed. This ASIC has been integrated with the VCSEL array in a customized optical module for the optical test. The test results show the wide-open 14 Gbps optical eye diagram with a measured RMS jitter of 2.7 ps and a peak-to-peak jitter of 17.4 ps, respectively.

A Wide-Lock-In-Range and Low-Jitter 12–14.5 GHz SSPLL Using a Low-Power Frequency-Disturbance-Detecting and Correcting Loop

This article presents a wide-lock-in-range and ultralow-jitter, 12-14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance, ${f_{{D}}}$ , frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency, ${f_{{REF}}}$ . Since the FDC loop only is concerned with correcting an ${f_{{D}}}$ -event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz ${f_{{REF}}}$ . In the measurements, the FDC loop that consumed only 150 μW of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm², and the total power consumption was 7.7 mW.

A 2.4–3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz.

A Calibration-Free Ring-Oscillator PLL With Gain Tracking Achieving 9% Jitter Variation Over PVT

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%.

A 5-Gb/s Adaptive Digital CDR Circuit With SSC Capability and Enhanced High-Frequency Jitter Tolerance

A 5-Gb/s digital clock/data recovery (DCDR) circuit with spread-spectrum clocking (SSC) capability and enhanced high-frequency jitter tolerance (JTOL) is presented. To track input data with both the frequency offset and the SSC, an integral gain controller is used to adjust an integral gain of the digital loop filter. It enhances the high-frequency JTOL. This DCDR circuit is fabricated in 40nm CMOS process. Its active area is 0.022mm2 and the power consumption is 9.9mW from a 1 V supply. With a 5-Gb/s PRBS of 27-1, the measured rms jitter of the retimed data is 9.47ps. For input data with the frequency offset of ±300ppm and SSC of -5000ppm, the measured minimum high-frequency JTOL is equal to 0.55 UIpp by using the proposed integral gain controller with a bit error rate (BER) $ .

A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TDC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , and the power consumption was 6.0 mW.

A fully linear 5.2 GHz - 5.8 GHz digitally controlled oscillator in 65-nm CMOS technology

A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The core chip occupied 400 μm × 702 μm area and consumed 2.1 mA current.

A Low Phase Noise Open Loop Fractional-N Frequency Synthesizer With Injection Locking Digital Phase Modulator

This brief presents a two stage open loop fractional-N frequency synthesizer using proposed injection locking phase modulator for low power applications. A novel low power injection locking oscillator (ILO)-based digital phase modulator (DPM) is proposed in this brief. The maximum differential nonlinearity (DNL) of proposed DPM is smaller than 0.3 degree in the whole range with 1.6 mW power consumption. An integer-N injection locking phase locked loop (ILPLL) is designed to generate the radio frequency signals for the second stage open loop frequency synthesizer. With an injection strength adjustment unit, the open loop fractional-N frequency synthesizer employing proposed DPM achieved excellent in band phase noise and instantaneous frequency switching with low power consumption. This frequency synthesizer is fabricated on 28-nm CMOS technology and its active area is 0.08 mm2. The output frequency range is from 320 MHz to 520 MHz and the power dissipation is 2.7 mW from 0.9 V supply in fractional-N mode. The measured RMS jitter integrated phase noise from 10 KHz to 40 MHz of 440 MHz and 440.4 MHz carrier frequency are 3.8 ps and 17.6 ps, respectively. The corresponding figure of merits (FoM) are −231 dB and −211 dB, respectively.

A $\Delta\Sigma$ Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

A spread-spectrum clock generator (SSCG) is an essential building block for reducing electromagnetic interference (EMI) in a system-on-a-chip without shielding the device that increases the system cost and weight. In a ${\Delta } {\Sigma }$ modulator (DSM)-based SSCG, EMI reduction is degraded by attenuating the harmonic components of the generated profile owing to the phase-locked loop bandwidth ( $ {f}_{{\text {LBW}}}$ ). This brief proposes a DSM-based SSCG with a digital compensator to maximize EMI reduction with a triangular profile. By adaptively reconfiguring the gains of the digital compensator, the proposed SSCG maintains the EMI reduction regardless of $ {f}_{\text {LBW}}$ variations. The EMI reduction is improved by 2.17 dB at 1.35 GHz with the lowest $ {f}_{\text {LBW}}$ . A prototype of the proposed SSCG is fabricated using 65-nm CMOS technology. The measured RMS jitter and power consumption are is 2.47 ps and 7 mW, respectively and the die occupies 0.292 mm2.

8–10 Gbit/s full synthesised continuous‐half‐rate reference‐less all‐digital CDR with sub‐harmonic frequency extraction

Continuous-rate all-digital reference-less clock and data recovery (CDR) circuit that utilises a sub-harmonic extraction scheme for wide-range frequency detection is presented. In the proposed CDR, the capture range of the frequency locked loop (FLL) is extended to the tuning range of digital controlled oscillator, thanks to the subharmonic extraction scheme. The frequency errors of FLL in lock state are within the tracking range of CDR loop. The prototype reference-less all-digital CDR, fabricated using a 40 nm CMOS technology, successfully detects 8–10 Gbit/s PRBS 231 − 1 data and produces the recovered clock. The CDR consumes 29 mW from a supply voltage of 1 V for 10 Gbit/s input data. The measured RMS jitter of the recovered clock is 2.24 ps.

A Fast-Lock Low-Jitter PLL Based Adaptive Bandwidth Technique

An adaptive-bandwidth phase-locked loop (PLL) presented in this paper is a multi-function, general purpose frequency synthesizer. Ultra-wide input and output ranges along with best-in-class jitter performance allow the PLL to be used for almost any clocking application. To reach wide output range and optimal jitter performance, adaptive bandwidth technique is applied to guarantee the stability of the loop. Furthermore, a fast-lock circuit is used to improve locking speed. The PLL is implemented in a 65nm CMOS process, while the core occupies 0.05mm2 and measurement results shows that the adaptive bandwidth PLL can generate clock with frequency from 200MHz to 1.6GHz. The measurement results also show good robustness of the PLL over temperature and supply voltage variation. The measured RMS jitters at 1.6GHz is less than 0.8ps when the supply noise under the 1% of itself. The fast-lock process lasts less than 3us, and the complete lock time is determined as 1000 input cycles.

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A low-jitter and low-reference-spur ring-type voltage-controlled oscillator (VCO)-based switched-loop filter (SLF) phase-locked loop (PLL) is presented. To enhance the capability of suppressing jitter of a VCO, we propose a fast phase-error correction (FPEC) technique that emulates the phase-realignment mechanism of an injection-locked clock multiplier. By the proposed FPEC technique, accumulated jitter of a VCO can be removed intensively in a short interval, thereby suppressing jitter dramatically. Based on a PLL topology having an intrinsic integrator in a VCO, the proposed architecture can also achieve a low reference spur despite a high multiplication factor (i.e., 64). This paper also presents the selective frequency-tuning technique used in the VCO that helps the proposed architecture further suppress the level of reference spur. The proposed PLL was fabricated in a 65-nm CMOS process. The measured rms jitter integrated from 1 kHz to 80 MHz and the reference spur of the output signal with a 3.008-GHz frequency were 357 fs and −71 dBc, respectively. The total active area was 0.047 mm2, and the power consumption was 4.6 mW.

A 51.3-MHz 21.8-ppm/°C CMOS Relaxation Oscillator With Temperature Compensation

A 51.3-MHz 18- $\mu\text{W}$ 21.8-ppm/°C relaxation oscillator is presented in 90-nm CMOS. The proposed oscillator employs an integrated error feedback and composite resistors to minimize its sensitivity to temperature variations. For a temperature range from −20 °C to 100 °C, the fabricated circuit demonstrates a frequency variation less than ±0.13%, leading to an average frequency drift of 21.8 ppm/°C. As the supply voltage changes from 0.8 to 1.2 V, the frequency variation is ±0.53%. The measured rms jitter and phase noise at 1-MHz offset are 89.27 ps and −83.29 dBc/Hz, respectively.

A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase–frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.

A low jitter supply regulated charge pump PLL with self-calibration**Project supported by the National Key Basic Research and Development Program of China (No. 2015CB352100).

This paper describes a ring oscillator based low jitter charge pump PLL with supply regulation and digital calibration. In order to combat power supply noise, a low drop output voltage regulator is implemented. The VCO gain is tunable by using the 4 bit control self-calibration technique. So that the optimal VCO gain is automatically selected and the process/temperature variation is compensated. Fabricated in the 0.13 μm CMOS process, the PLL achieves a frequency range of 100–400 MHz and occupies a 190 × 200 μm2 area. The measured RMS jitter is 5.36 ps at a 400 MHz operating frequency.

A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment

A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors. According to the detection results of ML-BBPD, the DGAC can adjust the dynamic integral gain of digital loop filter to provide four different operation modes and keep the ADPLL always in stable operation for fast-locking procedure. The DCO with loading compensation circuit can decrease the difference of tuning range in 13 bands less than 25%. Implemented with a 0.18- $\mu{\rm m}$ CMOS technology, the area of the core circuit is 0.7735 ${\rm mm}^{2}$ and the total power consumption is 35 mW from a 1.8 V supply voltage at 1.25 GHz. The ADPLL can generate output frequencies from 253.9 MHz to 1.367 GHz with 12-phase output clocks. Experimental result shows that the locking time can be accomplished in 2.9184 $\mu{\rm s}$ , i.e., 57 cycles with a 19.53125 MHz reference clock. The phase noise is $-$ 108.77 dBc/Hz at 1 MHz frequency offset, and measured rms jitter and peak-to-peak jitter are 8.884 ps and 32.5 ps respectively.

Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

This paper describes the clock distribution and synchronization network for a 64 bit ARMv8 8-core microprocessor. Embedded in a SoC for cloud computing platforms, the processor is fabricated in a 40 nm CMOS technology and operates at 3.0 GHz. The system PLL has a measured rms jitter <;1 ps and features dynamic frequency hopping for DVFS applications. In conjunction with a Star/H/Mesh topology, the clock distribution uses both CML and CMOS circuits to minimize period jitter and nominally achieves <;0.8 ps/mV | rms and <;9 ps of period jitter and skew, respectively. By using local Duty Cycle Adjustment circuits in each core to properly offset the clock duty cycle and ease timing critical paths, the processor performance improves by more than 5%. A simple probing circuit for high speed clock measurements can be used to monitor the high frequency excursions of the internal supply to counteract any timing violation that could occur. Finally an enhanced latch, which improves MTBF by up to 5 orders of magnitude and thus is suited for high speed synchronization operations, is proposed.