A Fast-Locking All-Digital Phase-Locked Loop With Dynamic Loop Bandwidth Adjustment

Abstract

A fast-locking all-digital phase-locked loop (ADPLL) including a fast-locking unit, a multi-level bang-bang phase detector (ML-BBPD), a dynamic gain adjustment controller (DGAC), and a digitally controlled oscillator (DCO) is presented. The ML-BBPD provides multi-level outputs with different phase errors. According to the detection results of ML-BBPD, the DGAC can adjust the dynamic integral gain of digital loop filter to provide four different operation modes and keep the ADPLL always in stable operation for fast-locking procedure. The DCO with loading compensation circuit can decrease the difference of tuning range in 13 bands less than 25%. Implemented with a 0.18- $\mu{\rm m}$ CMOS technology, the area of the core circuit is 0.7735 ${\rm mm}^{2}$ and the total power consumption is 35 mW from a 1.8 V supply voltage at 1.25 GHz. The ADPLL can generate output frequencies from 253.9 MHz to 1.367 GHz with 12-phase output clocks. Experimental result shows that the locking time can be accomplished in 2.9184 $\mu{\rm s}$ , i.e., 57 cycles with a 19.53125 MHz reference clock. The phase noise is $-$ 108.77 dBc/Hz at 1 MHz frequency offset, and measured rms jitter and peak-to-peak jitter are 8.884 ps and 32.5 ps respectively.