A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

Jun Zhao,Yong-Bin Kim

doi:10.1155/2010/946710

Abstract

A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM) at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

Highlights

Phase-locked loops are widely used in many communication systems for clock and data recovery or frequency synthesis [1,2,3,4,5]
This paper proposes a novel digitally controlled oscillator (DCO) circuit with significantly reduced power consumption using binary controlled pass transistors and Schmitt trigger inverters
The lock-in process of the proposed All Digital Phase-Locked Loop (ADPLL) is illustrated in Figure 17 when locking to 700 MHz

Summary

Introduction

Phase-locked loops are widely used in many communication systems for clock and data recovery or frequency synthesis [1,2,3,4,5]. Computers, televisions, radios, and motor speed controllers are just a few examples that rely on PLLs for proper operation. ADPLL will not have the same performance as its analog counterpart, it provides a faster lock-in time and better testability, stability, and portability over difference process [6, 7]. One technique changes the driving strength dynamically using the fixed capacitance loading [8, 9] while the other uses shunt capacitor technique to tune the capacitance loading [10] Both of the approaches have a good linear frequency response and a reasonable frequency operating range, the power dissipation has not been taken into consideration. The DCO frequency changes back to the reference clock by updating the control bits. The ADPLL with the proposed DCO was implemented using a 0.9 V 32 nm practical transistor model

DCO Principle and Design

Performance Verification of the Proposed DCO

Simulation Results of the ADPLL with the Proposed DCO

Conclusion