A 2.4–3.0GHz Process-Tolerant Sub-Sampling PLL With Loop Bandwidth Calibration

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A sub-sampling phase-locked loop (SSPLL) with loop bandwidth calibration is presented. By using a sub-sampling phase detector with gain calibration and a pulse width control circuit, the loop bandwidth deviation of the SSPLL can be reduced. This SSPLL is fabricated in a 40 nm CMOS process and its core area is 0.15mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The power consumption of the SSPLL is 5.81mW from a supply of 1.1V. The reference frequency is 75 MHz and the output frequency range of the SSPLL is 2.4~3.0GHz. The measured rms jitter is 2.02ps at the output frequency of 3.0GHz. With the calibration, the largest loop bandwidth deviation from 3.5MHz among five samples is reduced from -71.4% to -18.5% at 3.0GHz.