Abstract
To solve the noise and spurious problems of the Charge Pump Phase-Locked Loop (CPPLL), this paper presents a Sub-sampling Phase-Locked Loop (SSPLL), which has an output frequency of 64MHz with low noise and low spur. Subsampling technology is used to reduce the in-band noise of the SSPLL. By designing an excellent performance Sub-sampling Charge Pump (SSCP) and Sub-sampling Phase Detector (SSPD), the spur reference of the Voltage Controlled Oscillator (VCO) output clock and the mismatch of current are decreased. The SSPLL is implemented in SMIC 110nm CMOS process consuming 1.85mW from 1.2V supply and occupying an area of 0.12x0.10mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The in-band noise of the SSPLL at 10KHz is - 118.36dBc/Hz and the reference spur of the VCO output clock is -89.31dB.
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