Maximum Operating Frequency Research Articles

A Resource Constrained Neural Network for the Design of Embedded Human Posture Recognition Systems

A custom HW design of a Fully Convolutional Neural Network (FCN) is presented in this paper to implement an embeddable Human Posture Recognition (HPR) system capable of very high accuracy both for laying and sitting posture recognition. The FCN exploits a new base-2 quantization scheme for weight and binarized activations to meet the optimal trade-off between low power dissipation, a very reduced set of instantiated physical resources and state-of-the-art accuracy to classify human postures. By using a limited number of pressure sensors only, the optimized HW implementation allows keeping the computation close to the data sources according to the edge computing paradigm and enables the design of embedded HP systems. The FCN can be simply reconfigured to be used for laying and sitting posture recognition. Tested on a public dataset for in-bed posture classification, the proposed FCN obtains a mean accuracy value of 96.77% to recognize 17 different postures, while a small custom dataset has been used for training and testing for sitting posture recognition, where the FCN achieves 98.88% accuracy to recognize eight positions. The FCN has been prototyped on a Xilinx Artix 7 FPGA where it exhibits a dynamic power dissipation lower than 11 mW and 7 mW for laying and sitting posture recognition, respectively, and a maximum operation frequency of 47.64 MHz and 26.6 MHz, corresponding to an Output Data Rate (ODR) of the sensors of 16.50 kHz and 9.13 kHz, respectively. Furthermore, synthesis results with a CMOS 130 nm technology have been reported, to give an estimation about the possibility of an in-sensor circuital implementation.

An FPGA-Based Performance Evaluation of Artificial Neural Network Architecture Algorithm for IoT

Nowadays, the high number of devices and applications connected to the Internet has generated a great amount of data being which makes privacy and protection a more challenging task. In addition, new technologies, such as the Internet of Things, incorporate many resource-constrained devices in the network. Reliable cryptography algorithms have to be employed to deal with this problem, which also needs to be efficiently implemented in small devices. There are several algorithms for this purpose, among them, neural cryptography. In this context, this work proposes the implementation of an artificial neural network architecture called tree parity machine (TPM) to perform the exchange of keys through the mutual learning of these networks. This method is not based on number theory, which makes it less computationally costly, and can be an alternative for embedded systems, which generally have several limitations in the processing capacity and resources used. In the area of embedded systems, FPGAs have gained more space, thanks to their reconfiguration capacity. Thus, different methods for implementing a TPM in FPGA were tested and analyzed, in order to optimize the following performance parameters, the response time, the maximum frequency of operation, and the consumed area of the FPGA considering logical elements, embedded multipliers, and registers. In addition, software implementation based on a multi-core CPU was used for comparison purposes. Experimental results demonstrated that the implementation of parallelism in FPGA for different blocks of the TPM weight matrix reached the best performance results. Thus, our proposal intends to develop an economic component in terms of resource consumption, however, maintaining the characteristic of high processing capacity. Therefore, the methodologies presented in this paper intends to be a useful reference to optimize future implementations in FPGA for cryptography applications.

Improving Characteristics of LUT-Based Mealy FSMs with Twofold State Assignment

Practically, any digital system includes sequential blocks. This article is devoted to a case when sequential blocks are represented by models of Mealy finite state machines (FSMs). The performance (maximum operating frequency) is one of the most important characteristics of an FSM circuit. In this article, a method is proposed which aims at increasing the operating frequency of LUT-based Mealy FSMs with twofold state assignment. This is done using only extended state codes. Such an approach allows excluding a block of transformation of binary state codes into extended state codes. The proposed approach leads to LUT-based Mealy FSM circuits having two levels of logic blocks. Each function for any logic level is represented by a circuit including a single LUT. The proposed method is illustrated by an example of synthesis. The results of experiments conducted with standard benchmarks show that the proposed approach produces LUT-based circuits with significantly higher operating frequency than it is for circuits produced by other investigated methods (Auto and One-hot of Vivado, JEDI, twofold state assignment). The performance is increased by an average of 15.9 to 25.49 percent. These improvements are accompanied by a small growth of the numbers of LUTs compared with circuits based on twofold state assignment. Our approach provides the best area-time products compared with other investigated methods. The advantages of the proposed approach increase as the number of FSM inputs and states increases.

Efficient design of decimation filter using linear programming and its FPGA implementation

In this paper we present two-stage CIC (cascaded-integrator-comb) decimation filters with decimation factor M expressed as M = M1M2, where M1,M2∈Z+. The proposed decimator-I aims to minimize the pass-band droop using a cascade connection of Kaiser Hamming (KH) and Saramäki-Ritoniemi (SR) sharpening structures. The coefficients of second stage are determined using linear programming in MATLAB. The proposed CIC decimator-I when designed for various integer decimation factors on an average has a pass-band droop of −0.09 dB at the normalized frequency of 1/2 M and an average alias rejection of −44 dB at the normalized frequency of 3/2 M. Further, another decimator-II structure extends decimator-I to achieve an alias rejection of −87 dB and pass-band droop of −0.17 dB. The FPGA implementation of proposed designs has lower slice utilization and achieves higher maximum operating frequency than other existing competing designs. The performance of proposed decimation filters is confirmed using computer simulations in analog-to-digital converters (ADC) and sigma-delta (ΣΔ) modulators.

FPGA-based implementation of two-step schedulers for modular optical interconnection networks

Optical interconnection networks promise to overcome the limitations of current electronic switching fabrics, enabling higher throughput, lower latency, and lower power consumption. Multi-plane architectures, based on multiple optical switching domains (e.g., space, time, wavelength, orbital angular momentum), are gaining research attention because of their modularity and scalability compared to single-domain switches. An effective scheduler, namely, the two-step scheduler (TSS), has been proposed for multi-plane optical interconnection networks, exploiting their modularity to speed up computations while satisfying the peculiar scheduling constraints. In this paper, a hardware implementation of TSS for modular optical interconnection networks is presented and thoroughly assessed. Both scheduling steps are parallelized with the aim of optimizing the execution time. iSLIP and longest queue first (LQF) scheduling algorithms are exploited in each step, resulting in four TSS configurations that are compared among each other and with classical single-step schedulers (SSSs) in terms of scheduling and hardware performance. TSS outperforms SSS in terms of the number of iterations, maximum operating frequency, worst-case scheduling duration, and required logic resources (i.e., scalability) at the expense of a slight latency penalty. Among all TSS configurations, LQF-based TSS guarantees the lowest scheduling latency, while iSLIP-based TSS minimizes the scheduling duration and the use of field programmable gate array (FPGA) resources.

Demonstration of a 47.8 GHz High-Speed FFT Processor Using Single-Flux-Quantum Technology

A fast Fourier transform (FFT) is an algorithm that computes the discrete Fourier transform (DFT) of a sequence at high speed. FFT can convert a signal from time domain to frequency domain, and is wildly used in digital signal processing field. In this paper, a high-speed, low-power FFT processor is demonstrated up to 47.8GHz with the measured power consumption of 5.3mW, using single-flux quantum (SFQ) logic. This is the first complete FFT processor implementation using superconducting technology, performing 8-point 7-bit FFT in a bit-serial computing manner. The test chip fabricated using a 1.0 μm 9-layer process consists of 17 455 Nb/AlO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /Nb Josephson junctions (JJs), rendering itself the largest superconducting digital circuit capable of iterative data computing. The correct operation of the chip has been experimentally confirmed at a maximum operating frequency of 47.8GHz (word speed 8GHz) by conducting on-chip high-speed testing.

Threshold-Based Fast Successive-Cancellation Decoding of Polar Codes

Fast SC decoding overcomes the latency caused by the serial nature of the SC decoding by identifying new nodes in the upper levels of the SC decoding tree and implementing their fast parallel decoders. In this work, we first present a novel sequence repetition node corresponding to a particular class of bit sequences. Most existing special node types are special cases of the proposed sequence repetition node. Then, a fast parallel decoder is proposed for this class of node. To further speed up the decoding process of general nodes outside this class, a threshold-based hard-decision-aided scheme is introduced. The threshold value that guarantees a given error-correction performance in the proposed scheme is derived theoretically. Analysis and hardware implementation results on a polar code of length 1024 with code rates 1/4, 1/2, and 3/4 show that our proposed algorithm reduces the required clock cycles by up to 8%, and leads to a 10% improvement in the maximum operating frequency compared to state-of-the-art decoders without tangibly altering the error-correction performance. In addition, using the proposed threshold-based hard-decision-aided scheme, the decoding latency can be further reduced by 57% at E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">b</sub> /N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> = 5.0 dB.

Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption

Bicubic interpolation is widely used in real-time image processing systems because of its quality. The real-time implementation of bicubic interpolation requires a lot of hardware resources, especially the number of multipliers because it represents high computational complexity. In this article, a set of algorithms that approximate the bicubic interpolation and reduce the hardware resource consumption are proposed. The proposed algorithms are based on combining linear and cubic interpolations. These algorithms are surveyed and compared in terms of interpolation quality, number of adders, number of multipliers, adaptive logic modules, lookup tables (LUTs), registers, and maximum operating frequency. These algorithms are implemented and tested on an Intel Cyclone V target. This article provides various choices of interpolation algorithms to cater to different application requirements, including accuracy, hardware resource consumption, and throughput performance. The implementation codes are available at github.com/DreamIP/Interpolation.

A Novel Dormand-Prince Based Hybrid Chaotic True Random Number Generator on FPGA

This study presents a novel Dormand-Prince-based hybrid chaotic True Random Number Generator Design (TRNG) that can be used for secure communication and cryptographic applications on Field Programmable Gate Array (FPGA). In this design, a chaotic oscillator unit has been implemented with an FPGA-based Sprott-Jafari chaotic oscillator model suitable with IQ-Math fixed point number and IEEE 754-1985 floating point number standards. Random numbers have been produced with the quantization of the results generated by the chaotic oscillator. XOR has been performed with FPGA-based ring oscillator structure on the post-processing unit so as to enhance the randomness. The differential equation of the chaotic system used in the TRNG design was modelled using Dormand-Prince numerical algorithm method. The design on FPGA has been realized in two separate number formats including 32-bit (16I-16Q) IQ-Math fixed point number standard and 32-bit IEEE 754-1985 floating point number standard. The realized designs have been coded in VHDL, a hardware description language, and the Xilinx ISE 14.7 program has been used for the system design. Two separate TRNG designs have been synthesized and tested for the Virtex-6 (XC6VLX240T-1FF1156) FPGA chip. The maximum operating frequency of the TRNG with 32-bit IQ-Math fixed point number standard is 344.585 MHz and the throughput is approximately 344 Mbit/s. The maximum operating frequency of the TRNG with 32-bit IEEE 754-1985 floating point number standard is 316.756 MHz and the throughput is 316 Mbit/s. 1 Mbit sequence has been generated by both designed TRNG systems. Randomness analysis of the generated numbers has been performed in accordance with the NIST 800-22 tests and the generated numbers have successfully passed all of the tests.

Low-power high-speed half-flux-quantum circuits driven by low bias voltages

Half-flux-quantum (HFQ) circuits store and propagate half-flux quanta. The basic circuit element is a 0-π SQUID, which is a superconducting quantum interference device with a conventional Josephson junction (0-junction) and a π-shifted ferromagnetic junction (π-junction). A 0-π SQUID achieves a small critical current in the absence of an external magnetic field, thus reducing power consumption. It is easy to set up 0-0-π SQUIDs with two 0-junctions and a π-junction which serves as a π phase-shifter. We simulated 0-0-π SQUID-based HFQ circuits driven by low bias voltages, referred to as LV-HFQ circuits. In these circuits, shunt resistors are not required for switching junctions because there is no hysteresis in the current–voltage characteristics of 0-0-π SQUIDs. We estimated the power consumption and maximum operating frequency of an HFQ Josephson transmission line based on 0-0-π SQUIDs. When operating at 43.5 GHz, the power dissipation of a single element composed of a 0-0-π SQUID and a bias resistor fell to about 0.165 nW when biased at 60 μV. The LV-HFQ circuit is potentially more power-efficient than all other currently available superconducting logic circuits.

Design of digital pulse width modulator architecture with digital PID controller for DC-DC converter using FPGA

A digital pulse width modulation architecture (DPWM) along with digital proportional integral derivative (PID) controller to control the DC-DC converter is presented in this paper. Difference between the actual output voltage and the reference voltage is calculated as error value. The look up table is created for PID controller to store the duty cycle ratio and the error value of power converters. Multipliers used in conventional algorithms are replaced by look up tables in the proposed work that enable the compact and low power implementation of digital controllers. DPWM architecture is developed with gray logic against the binary logic used in traditional DPWM architectures. Usage of gray counter also leads to low power consumption in the DPWM architecture. The proposed architecture is designed using Verilog hardware language and realized using field programmable gate array. PWM signals with varying duty cycle percentage can be derived from the proposed architecture. The generated PWM signal can control the switching condition of power converter to regulate the output voltage. Duty cycle percentage ranging from 16 to 96% can be developed with the proposed architecture. Simulation and experimental results of the architecture validate the proposed architecture. PWM signal with maximum operating frequency of 59.49 MHz and 60.22 MHz for SPARTAN 3A and SPARTAN 3E respectively can be generated with the proposed architecture.

A Digital-Analog Hybrid System-on-Chip for Capacitive Sensor Measurement and Control.

Sensors based on capacitance detection are common in the field of inertial measurement and have the potential for miniaturization and low power consumption. In order to control and process such sensors, a novel digital-analog hybrid system-on-chip (SoC) is designed and implemented. The system includes a capacitor to voltage (C/V) conversion circuit and a band-pass sigma-delta modulator (BPSDM) as the analog-to-digital converter (ADC). The digital signal is processed by the dedicated circuit module based on the least mean square error demodulation (LMSD) algorithm on the chip. The low-power Cortex-M3 processor supports software implementation of control algorithms and circuit parameter configuration. The control signal is output through a digital BPSDM. The chip was taped out under SMIC 180 nm Complementary Metal Oxide Semiconductor (CMOS) technology and tested for performance. The result shows that the maximum operating frequency of the chip is 105 MHz. The total area is 77.43 mm2. When the system clock is set to 51.2 MHz, the static power consumption and dynamic power consumption of the digital system are 18 mW and 54 mW respectively.

Comparison of parameters of ring and LC-tank digitally controlled oscillators in 0.13 µm CMOS

Abstract Integrated circuits (IC) of two digitally controlled oscillators (DCO) are presented in this article – ring and LC-tank oscillator. Main parameters of these DCOs are measured and compared, applications of such DCOs are discussed. Ring DCO is made of 48 sections of 3-stage ring oscillators. Base component of ring oscillator is tristate inverter, which is accessible in modern CMOS technologies, therefore, such oscillator can be implemented using digital IC design tools. Main components of LC-tank DCO are inductor, switched-capacitor bank, and a pair of cross-coupled NMOS transistors. Frequency of ring DCO is controlled by enabling or disabling its separate sections, while frequency of LC DCO is controlled by switching capacitors of LC tank. Although LC DCO is controlled digitally, its core is analog and it can be implemented only using custom design tools. Both DCOs are designed and their prototypes are manufactured in mature and low-cost 0.13 μm RF CMOS technology. Ring DCO’s frequency tuning range is 370–873 MHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is – 109.19 dBc/Hz; power consumption is 3.6 mW; used area of silicon is 0.0065 mm2. LC-tank DCO’s frequency tuning range is 9.26–10.58 GHz; phase noise at maximum operating frequency at 1 MHz offset from carrier is –106.46 dBc/Hz; power consumption is 18 mW; used area of silicon is 0.06 mm2. Operating frequency of LC-tank DCO is much higher, however Figures of Merit of ring and LC-tank DCOs are comparable and respectively equal to –140.61 dBc/Hz and –136.88 dBc/Hz. It shows, that both DCOs can be used in modern systems for appropriate applications. Main applications of LC-tank DCO are high-speed systems, where high frequency is needed, while in low-cost, low-power systems ring DCO is more suitable.

Design and development of a low cost Arduino controlled ethernet interfaced Majority Logic Unit

Design and development of an Arduino based control system and a Majority Logic Unit have been presented, which can perform different logic operations in remote as well as in manual mode. Performances of this unit viz. time jitter, minimum overlap time, maximum operating frequency, double pulse resolution and module delay have been measured which are found to be comparable with the commercially available modules. This work presents a low cost up-gradation of the commercially available manually controlled Majority Logic Units.

Gain and bandwidth of InP nanowire array photodetectors with embedded photogated InAsP quantum discs.

Here we report on the experimental results and advanced self-consistent real device simulations revealing a fundamental insight into the non-linear optical response of n+-i-n+ InP nanowire array photoconductors to selective 980 nm excitation of 20 axially embedded InAsP quantum discs in each nanowire. The optical characteristics are interpreted in terms of a photogating mechanism that results from an electrostatic feedback from trapped charge on the electronic band structure of the nanowires, similar to the gate action in a field-effect transistor. From detailed analyses of the complex charge carrier dynamics in dark and under illumination was concluded that electrons are trapped in two acceptor states, located at 140 and 190 meV below the conduction band edge, at the interface between the nanowires and a radial insulating SiOx cap layer. The non-linear optical response was investigated at length by photocurrent measurements recorded over a wide power range. From these measurements were extracted responsivities of 250 A W-1 (gain 320)@20 nW and 0.20 A W-1 (gain 0.2)@20 mW with a detector bias of 3.5 V, in excellent agreement with the proposed two-trap model. Finally, a small signal optical AC analysis was made both experimentally and theoretically to investigate the influence of the interface traps on the detector bandwidth. While the traps limit the cut-off frequency to around 10 kHz, the maximum operating frequency of the detectors stretches into the MHz region.

Design of RF Planar Slow Wave Interaction Structure for THz Devices

Micro fabricated planar slow wave structure (SWS) in a travelling wave tube (TWT) has shown a superior performance when compared with the circular helix structure for RF power amplification. The circular helix structure applications are limited to the maximum operating frequency of 70 GHz. In the proposed paper, a rectangular planar slow wave structure operating at terahertz (THz) is designed. Fabrication of the beam interaction system is complex especially operating at higher frequencies as the device dimensions decrease. Use of planar interaction system simplifies the miniaturised fabrication process. The present paper focused on the design of staggered double vane slow wave structure (SWS) and simulated the corresponding dispersion diagram and S-parameters of the model by using CST Studio Suite software. The results for designed RF planar slow wave structure are then analysed.

CCII current conveyor and dormand-prince-based chaotic oscillator designs for secure communication applications

Chaos is one of the important research areas in recent years. The chaotic signal generator is one of the most basic structure in the chaos-based researches and applications. In this study, Sundarapandian-Pehlivan Chaotic Oscillator (SPCO) designs have been implemented in 2 different platforms as analog-based using Second-Generation Current Controlled Current Conveyor (CCII) and FPGA-based with one of the chaotic oscillator that has been presented to the literature namely Sundarapandian-Pehlivan system. The structure used for the design of CCII-based chaotic oscillator and the results obtained from the study have been presented. In the second phase, the design of SPCO has been realized in order to utilize for running in FPGA chips using Dormand-Prince (DP) numeric algorithm. The design has been coded in VHDL using 32-bit IEEE-754-1985 floating point representation. The designed system has been tested by synthesizing it in Xilinx ISE Design Tools program. Then, the test results obtained from DP-based SPCO structure have been presented. In the last phase, the designed system has been synthesized for VIRTEX-7 FPGA. FPGA chip resource consumption values that obtained after the Place-Route process are presented. According to the results, the maximum operating frequency of DP-based SPCO unit on FPGA is obtained as 362.608 MHz. In future studies, the designs of Pseudo Random Number Generator (RNG) and True RNG can be performed using DP-based SPCO unit implemented successfully in this study.

Design and Implementation of a Lossless Compression System for Hyperspectral Images

Despite its popularity, the hyperspectral image compression algorithm recommended by the Consultative Committee for Space Data Systems (CCSDS) faces a long delay of the feedback loop and complex computations in the modes of band sequential (BSQ) and band interleaved by line (BIL). After analyzing the features of the CCSDS algorithm, this paper proposes a forward prediction method based on the xc7k325tffg9000 field programmable gate array (FPGA) chip (Xilinx Inc.), and adjusts the calculation flow of the CCSDS algorithm, aiming to shorten the time delay in the feedback loop. In addition, full-pipeline construction was implemented on FPGA board to realize real-time processing of data, and dynamic configuration of image parameters. Through functional simulation and off-board test, it is learned that, for the speed-insensitive path, the optimized algorithm can realize the complex operations of the original algorithm with less hardware resources; for hyperspectral image data with an effective input bit width of 12bit, the proposed method can reach a maximum operating frequency of 103MHz, and the data throughput of 103M samples per second (1.237Gbps).

Performance Investigation of Silicon-on-Insulator Junctionless Drain Extended FinFET for High Power, Radio Frequency Applications

This research article explores the scope of Silicon-On-Insulator (SOI) Junctionless (JL) Drain Extended (De) FinFET and compared it with Conventional SOI Drain Extended FinFET (Conv. SOI DeFinFET) for high power and high frequencies applications. The device simulation is performed by three dimensional (3D) simulations by sentaurus TCAD tool to optimize the device parameters at 14 nm gate length including the height (Hfin), the width (Wfin) and channel doping (Nch) of the fin of both devices. Both devices are compared in terms of drain current (DC) characteristics (breakdown voltage, on-resistance and drain current) and radio frequency (RF) characteristics (trans-conductance, current gain, cut-off frequency, power gain and maximum operating frequency). The results reveal that the proposed JL SOI DeFinFET is also one of the contenders with Conv. SOI DeFinFET for the regime of high power and high frequency.

A Linear Inchworm Piezomotor with a New Configuration: Design Considerations, Fabrication and Characterization

The new technologies of precise positioning systems with high speed and accuracy have been in the focus of attention in the recent years. In this research, a one-axis walker type inchworm piezomotor has been designed, modeled, manufactured and characterized. Simple design, simple manufacturing and assembly processes, low manufacturing cost and also high speed and stroke are advantages of this piezomotor. This system consists of three piezoelectric actuators, which installed into the clamps and feeder sets, and a guideway. The geometrical parameters with a high impact on the stiffness have been realized and modeled by the finite element method to ensure the proper functioning of the piezomotor. The motor dimensions are 55 × 23.1 × 15 mm3 which can provide a large movement range inside the guideway. The simulation analysis and experimental tests have been carried out to characterize the piezomotor. Based on the shape mode analysis, the maximum operating frequency of the piezomtor has been determined. Also, the Von-Mises stress analysis has been employed to predict the structural behavior of the motor. Finally, the experimental tests have been conducted to illustrate the piezomotor characteristics such as step pitch, speed, and operating frequency.