MATLAB Xilinx System Generator Research Articles

The design and implementation of folded adaptive lattice filter structures in FPGA for ECG signals

An adaptive filter is the utmost essential filter castoff in statistical signal dealing. The fine-tuning of the filter factor in relation to the response signal is the adaptive filter's key feature due to fewer calculations, Least Mean Square (LMS) adaptive filters are widely used to remove noise from Electrocardiograms (ECG). The adaptive filters are realized as signal processing algorithms in Digital Signal Processors (DSPs) or in VLSI Signal Processors (VSPs). The technique provides a way to create a folded adaptive lattice LMS filter, which requires less hardware than an adaptive lattice filter. Folding is an algorithm that uses a time scheduling technique that combines arithmetic operations into one operation which reduces Register and silicon chip areas. The design and implementation of a folded lattice adaptive filter remove Power Line Interference (PLI) noise from ECG signals. The MATLAB Xilinx System Generator tool is used to design the Adaptive Lattice LMS Filter and Folded Adaptive Lattice LMS Filter with Folding Order K = 2 and K = 4 and realized in the Virtex 5 FPGA KIT. The results of the folded architecture show that the area is reduced for K = 2 and K = 4 by 82.60% and 91.05%, respectively compared with a normal adaptive lattice filter.

Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Space Vector Pulse-Width Modulation (SVPWM) has now become an unavoidable PWM in the power electronics inverter development. If the SVPWM implementation can be made user-friendly, the operation can be easily soaked in by the future researchers and also the closed loop operation becomes sophisticated. This paper conveys a broad view about the state of art of different Field programmable gate array (FPGA) processors along with the inner views about the implementations of the 3-level SVPWM. The description of the different processors is discussed along with the implementation variance and also attempts to implement the SVPWM through Xilinx Spartan-III 3AN-XC3S400 using MATLAB-Xilinx System Generator (XSG) without deploying the direct Very High Speed Language (VHDL) code. It provides shortest translation designs into hardware implementations that are faithful, synthesizable and efficient, which permits the designer to minimise the time spent for the description and implementation of circuit. The synthesis result shows that the proposed implementation at 50 MHz frequency operation consumes a power of 13mW and occupies 1112 look up tables (LUTs) and 424 File File (FFs). Thereby, the Total Resource Utilization reduced drastically to 36%, which is far better than the other existing implementations. Also, the inference of less processing time can be seen from the synthesis.

A Simple Multilevel Space Vector Modulation Technique and MATLAB System Generator Built FPGA Implementation for Three-Level Neutral-Point Clamped Inverter

The pulse width modulation (PWM) is an important segment in power electronic inverters and multilevel inverters (MLIs) design. The space vector modulation (SVM) methods own distinct advantages over other PWM methods. However, MLI SVM has involved more mathematics in their executions. Hence, the digital signal processors (DSPs) or field programmable gate arrays (FPGAs) based digital implementations are highly preferred for MLI SVM realizations, which require exceptional properties. The conventional MLI SVMs use complex mathematical functions to solve their internal functions to identify the space vector diagram (SVD) sub-triangle and over modulation boundary switching on-times. Particularly these are the changes in the position of reference vector with respect to their sub-triangle positions involving higher mathematical functions. This paper proposes a simplified three-level MLI SVM that reduces the sub-triangle and over modulation switching on-time calculations with reduced mathematical functions. The proposed MLI SVM is derived based on two-level SVM without changing the reference vector position, unlike the traditional approaches. This helps in extending the SVM for any n-level inverter with additional LUTs. The detailed theoretical study, MATLAB-Simulink system generator simulations and Xilinx FPGA family SPARTAN-III-3A based experimental implementations are done with three-level neutral point MLI fed induction motor drive. The theoretical design, analysis, and experimentation results validate the advantages of the proposed PWM design and its implementation. In addition, the proposed implementation is executed from the MATLAB Xilinx system generator directly into target FPGA, which makes it faithful, efficient and minimizes the time spent.

FPGA Implementation of Digital Images Watermarking System Based on Discrete Haar Wavelet Transform

In this paper we propose a novel and efficient hardware implementation of an image watermarking system based on the Haar Discrete Wavelet Transform (DWT). DWT is used in image watermarking to hide secret pieces of information into a digital content with a good robustness. The main advantage of Haar DWT is the frequencies separation into four subbands (LL, LH, HL, and HH) which can be treated independently. This permits ensuring a better compromise between robustness and visibility factors. A Field Programmable Gate Array (FPGA) that is based on a very large scale integration architecture of the watermarking algorithm is developed to accelerate media authentication. A hardware cosimulation strategy using the Matlab-Xilinx system generator (XSG) was applied to prove the validity of the suggested implementation. The hardware cosimulation results show the effectiveness of the developed architecture in terms of visibility and robustness against several attacks. The proposed hardware system presents also a high performance in terms of the operating speed.

Instantaneous d frame driven shunt active filter for harmonics and reactive power mitigation using Xilinx System Generator

Instantaneous d frame driven Shunt active filter (SAF) alleviate harmonics and reactive power. This control algorithm evolved from elemental synchronous reference frame engenders the fundamental reference signal from the load current with a phase shift of zero angle. The proposed algorithm is tested in harmonic load and reactive load and it is verified by implementing the model in MATLAB Xilinx system generator. The comparison study was carried out for the proposed algorithm and conventional algorithm and the results are presented in this paper.

Digital Control of Three-Phase Cascaded Multilevel Inverter Using FPGA Wavect Tool

<span>The multi carrier modulation technique is the most employed PWM technique for cascaded multilevel inverter (CMLI) since this control strategy can be easily extended to higher number of levels of output compared to space vector PWM technique. This paper proposes a modified multi carrier PWM technique for three-phase CMLI. The proposed PWM technique has been implemented using MATLAB Xilinx System Generator, which automatically generate code from system model. The hardware implementation of the three-phase CMLI has been carried out to substantiate the working of proposed PWM technique. Novel FPGA Wavect digital controller is used to generate the PWM pulses, which is a real time simulator and controller. This digital controller improves the accuracy of the hardware implementation. Hardware implementation of proposed control strategy for three-phase CMLI with RL load proves that the proposed PWM technique results in improved power output quality with reduced harmonic components.</span>

Control System Implementation on an FPGA Platform

Abstract: This paper presents PID and SMC control schemes on a Field Programmable Gate Array device (FPGA) for robot manipulators. The implementation of the control systems on FPGA by using optimal hardware resources is one of the challenging research areas in control engineering. To accomplish this, MATLAB Xilinx System Generator toolbox plays an important role in control design on an FPGA device. In this paper, FPGA-based PD and SMC controllers are designed by using MATLAB Xilinx System Generator tool for the chosen robot system. The tracking performances of the presented control schemes, implemented in Matlab/Simulink and implemented on FPGA, are compared. Robustness and good trajectory performance of the system on FPGA are demonstrated.

Design and Simulation of Quadrature Phase Detection in Electrical Capacitance Volume Tomography

Capacitance measurement accuracy is affected by phase conformity between signal and reference. This work describes phase detection scheme which is necessary for phase synchronization in tomography application. Core processing for calculating phase and amplitude of the detected signal was built on FPGA (Field-Programmable Gate-Array) platform. Phase shift demodulation algorithm employs IP core provided by Xilinx FPGA. Direct digital synthesizer (DDS), multiplier, accumulator, and CORDIC (coordinate rotation digital computer) modules were used as excitation-reference signal generator, signal multiplication, accumulation, and conversion to polar coordinate in order to conduct trigonometric operation respectively. Hardware design was emulated on MATLAB-Xilinx System Generator to observe its performance. Phase detection range 0-114.58 o and mean absolute error 0.58 o have been achieved. Data processing rate solely at digital signal stage was approximately 100data/s suitable for 32-channel electrical capacitance volume tomography (ECVT) system.

LABTM Control System Based on FPGA

This paper presents the digital PI control method for design and simulation of a high precision limited angle brushless torque motor control system in Field Programmable Gate Array device (FPGA). The direct drive structures which are widely applied in many servo control fields. Matlab Xilinx System Generator® toolbox based on Fixed-Point Arithmetic is used to design the digital PI controller using DSP architecture, plot the responses of the control system and generate the VHDL source code. The control system model consists of a digital PI, a real LABTM, and a real absolute Inductosyn, encoder to rpm and position blocks. Through loading generated codes in process of the simulation that built by the digital discrete model, it is verified that the rising time of current loop is only 1.2ms, and rate loop is 8ms, overshoot is rarely 4.2%. Finally, the comprehensive positioning accuracy of system can reach up to ±5 arc sec, and the rate jitter achieves 5% with the ±4 arc sec accuracy absolute Inductosyn.