Minimum device usages of field programmable gate array (FPGA) verification of multilevel PWM inverter drive generation

Abstract

Space Vector Pulse-Width Modulation (SVPWM) has now become an unavoidable PWM in the power electronics inverter development. If the SVPWM implementation can be made user-friendly, the operation can be easily soaked in by the future researchers and also the closed loop operation becomes sophisticated. This paper conveys a broad view about the state of art of different Field programmable gate array (FPGA) processors along with the inner views about the implementations of the 3-level SVPWM. The description of the different processors is discussed along with the implementation variance and also attempts to implement the SVPWM through Xilinx Spartan-III 3AN-XC3S400 using MATLAB-Xilinx System Generator (XSG) without deploying the direct Very High Speed Language (VHDL) code. It provides shortest translation designs into hardware implementations that are faithful, synthesizable and efficient, which permits the designer to minimise the time spent for the description and implementation of circuit. The synthesis result shows that the proposed implementation at 50 MHz frequency operation consumes a power of 13mW and occupies 1112 look up tables (LUTs) and 424 File File (FFs). Thereby, the Total Resource Utilization reduced drastically to 36%, which is far better than the other existing implementations. Also, the inference of less processing time can be seen from the synthesis.