Output Matching Research Articles

Compact Layout Redesign of Output Matching Network of a 5.8-GHz SiGe Power Amplifier

This letter presents a general design methodology for compact layout of lumped element radio frequency (RF)/microwave matching networks based on partially overlapped inductors. We demonstrate the compact layout design approach on the output matching network of a TowerJazz 5.8-GHz SiGe power amplifier (PA) IP block fabricated in the 180-nm SBC18QH process. Our redesigned matching network achieves approximately a 20% footprint reduction. Small-signal measurements of PAs with original and compact output matching network designs, respectively, show virtually identical broadband performance.

Microwave Photonic ICs for 25 Gb/s Optical Link Based on SiGe BiCMOS Technology

The design, simulation and experimental results of the integrated optical and electronic components for 25 Gb/s microwave photonic link based on a 0.25 µm SiGe:C BiCMOS technology process are presented. A symmetrical depletion-type Mach-Zehnder modulator (MZM) and driver amplifier are intended for electro-optical (E/O) integrated transmitters. The optical divider and combiner of MZM are designed based on the self-imaging theory and then simulated with EM software. In order to verify the correctness of the theory and material properties used in the simulation, a short test (prototype) MZM of 1.9 mm length is produced and measured. It shows an extinction ratio of 19 dB and half-wave voltage-length product of Vπ ∙ L = ~1.5 V·cm. Based on these results, the construction of the segmented modulator with several driver amplifier units is defined. The designed driver amplifier unit provides a bandwidth of more than 30 GHz, saturated output power of 6 dBm (output voltage of Vpp = 1.26 V), and matching better than −15 dB up to 35 GHz; it dissipates 170 mW of power and occupies an area of 0.4 × 0.38 mm2. The optical-electrical (O/E) receiver consists of a Ge-photodiode, transimpedance amplifier (TIA), and passive optical structures that are integrated on a single chip. The measured O/E 3 dB analog bandwidth of the integrated receiver is 22 GHz, and output matching is better than −15 dB up to 30 GHz, which makes the receiver suitable for 25 Gb/s links with intensity modulation. The receiver operates at 1.55 μm wavelength, uses 2.5 V and 3.3 V power supplies, dissipates 160 mW of power, and occupies an area of 1.46 × 0.85 mm2.

Iterative matching-based parameter estimation for time-scale underwater acoustic multipath echo

In this paper, a wideband underwater acoustic multipath channel is investigated with a sonar-target relative movement. The underwater environment causes time delay, amplitude and Doppler factor changes on the transmitted signals, as a result, the signal components from the respective paths may be differentiated from these parameters. The Doppler factor of a specific path is analyzed in a moving condition, and the impulse responses of the propagation paths are illustrated by the wideband ambiguity function. Since different Doppler factors should be taken into consideration, an effective iterative method is proposed for parameter estimation of multipath echo. The proposed method retrieves a signal component by searching for the optimal scale factor from the resampling matching outputs, and eliminates the matching output of the estimated signal to analyze the next component. The effectiveness of the method is confirmed by some simulation results. It is also effective for various wideband signals with a broad range of frequencies, because the method prevents the time-domain subtractions of the received signals for providing a higher robustness. Therefore, it can be applied in many fields including active target detection and underwater communication.

Design of a compact chip filter with two transmission zeros using 0.35 μm GaAs HBT

This paper presents a very compact bandpass filter with two transmission zeros using a commercial GaAs HBT technology. The filter is constructed with two shunt LC tank to generate poles to ensure its passband characteristics, and two series LC tanks to generate zeros at lower and upper stopbands to improve the sideband rejection properties. An additional inductor and capacitor coupling network is employed to achieve good input and output matching without degeneration of the filter selectivity. The filter is designed and fabricated on a 0.35 μm GaAs HBT technology with a chip size of only 0.75 × 0.54 mm2. The test results demonstrated that, the center operation frequency of the proposed BPF is 3.45 GHz with a 500 MHz 1-dB bandwidth, the insertion loss is about 2.5 dB, and the sideband rejection is lower than −20 dB at the designed transmission zero frequencies.

X-Band High-Efficiency Continuous Class B Power Amplifier GaN MMIC Assisted by Input Second-Harmonic Tuning

This paper presents a high-efficiency continuous class B power amplifier MMIC (Monolithic Microwave Integrated Circuit) from 8 GHz to 10.5 GHz, fabricated with 0.25 μm GaN-on-SiC technology. The Pedro load-line method was performed to calculate the optimum load of the GaN field-effect transistor (FET) for efficiency enhancement. Optimized by an output second-harmonic tuned network, fundamental to second-harmonic impedance, mapping was established point-to-point within a broad frequency band, which approached the classic continuous class B mode with an expanded high-efficiency bandwidth. Moreover, the contribution to the output capacitance of the FET was introduced into the output second-harmonic tuned network, which simplified the structure of the output matching network. Assisted by the second-harmonic source-pull technique, the input second-harmonic tuned network was optimized to improve the efficiency of the power amplifier over the operation band. The measurement results showed 51–59% PAE (Power Added Efficiency) and 19.8–21.2 dB power gain with a saturated power of 40.8–42.2 dBm from 8 GHz to 10.5 GHz. The size of the chip was 3.2 × 2.4 mm2.

40-nm CMOS 공정을 이용한 220～260 GHz 대역 주파수 체배기 설계

In this paper, we present the design of a frequency doubler to generate a signal in the range of 220～260 GHz for 40-nm complementary metal oxide semiconductor(CMOS) technology. The circuit is composed of input, inter-change, and output matching as well as Marchand balun circuits in the form of microstrips. For an input frequency of 110～130 GHz, the doubler generates an output power between −6.5 dBm and −13 dBm with an output frequency of 220～260 GHz. The circuit consumes a power of only 0.66 mW with a supply voltage of 1.1 V. The dimensions of the chip, including pads, are 477μm× 486μm.

2.5～6 GHz 20 W급 광대역 GaN HEMT 내부 정합 전력증폭기

In this study, we designed and fabricated a 20-W internally matched gallium nitride(GaN) high-electron-mobility transistor(HEMT) power amplifier for an electronic warfare jammer in the frequency band of 2.5～6 GHz. The CGH60030D GaN HEMT from Wolfspeed was used as an amplifying device, and lossy matching was applied. An input series resistor that was used at the gate side for wideband matching reduced the amplifier’s low-frequency gain and minimized high-frequency loss in the design frequency band. Input and output matching circuits were implemented on two different substrates whose relative dielectric constants were 40 and 9.8, respectively. The fabricated internally matched power amplifier showed a linear gain of approximately 11.5 dB, a power-added efficiency of 35.6～40.5 %, and a power gain of 7.2～8.8 dB at an output power of 20 W from 2.5 to 6 GHz.

Co-Design of Matching Sub-Networks to Realize Broadband Symmetrical Doherty With Configurable Back-Off Region

In this brief, a technique using the co-design of three matching sub-networks is proposed to solve the contradiction between bandwidth and extended the back-off region of symmetrical Doherty power amplifier (DPA). The phase-shifting solution space of DPA output matching networks is calculated, and its relationship with the input impedance of the post-matching network is analyzed with and without the frequency variable. Configurable back-off region and adjustable operating center frequency can also be realized in the design by using the proposed method. The design flow is given, and then a detailed example under 9-dB back-off region is presented. To verify the proposed theory, a DPA is designed and fabricated across 1.9-2.4 GHz. The experimental results show drain efficiencies of 44.2-49.7% at 8.5-9 dB output power back-off levels across 1.9-2.4 GHz. The fabricated DPA achieves output powers of 44.1-44.8 dBm.

Design of a 10 W high‐efficiency balanced power amplifier using a combination of load‐pull and load‐line methods for ISM band

In this article, a 10 W power amplifier has been designed and constructed at 2.4 GHz. The source and load-pull impedance data published by the manufacturer at a nearby frequency of 2.5 GHz have been adopted to power match the transistor at the intended design frequency. For this purpose, the linear model of the GaN transistor has been derived from the S-parameter data. The load-line at the dependent current source plane and the impedance at the intrinsic gate-source capacitance have been simulated in the presence of the source and load-pull impedances at 2.5 GHz. The extracted impedances have been retained in the design of the power amplifier at 2.4 GHz. In a novel approach, the input and output matching circuits interacted with the linear model of the transistor to provide the same load-line conditions at the virtual drain plane and the intrinsic gate-source capacitance plane. In contrast to conventional load-pull methods that give no information about the harmonic terminations, harmonic terminations can be easily controlled in this method. The insight into the transistor linear model allows the harmonic terminations at the virtual drain plane to be set to low values for proper class-B operation.

Class-J23 Power Amplifiers

This paper presents the theoretical introduction and experimental validation of the “Class-J2 Mode Power Amplifier,” which provides higher efficiency and output power compared with conventional class-J mode counterpart. This mode of operation is realized by injection of the second-harmonic current to drain node of a class-J power amplifier (PA) to reduce the 45° phase shift between drain current and voltage signals. Similar to class-J PAs, the second-harmonic impedance of class-J2 PAs is purely reactive to simplify the design of the output matching network. The auxiliary second-harmonic injection circuit comprises a transistor biased in class-B mode followed by a class-C biased amplifier to achieve high second-harmonic current conversion efficiency. Theoretical formulations suggest that a 5% improvement in drain efficiency ( $\eta _{D}$ ) as well as a 1.5-dB increase in output power can be achieved for the class-J2 mode in comparison with the typical class-J operation. To check the accuracy of theoretical predictions, a proof-of-concept 1-GHz class-J2 PA with 12.2-dBm output power and 43% PAE is implemented in a 0.18- $\mu \text{m}$ CMOS technology. For better comparison, a 1-GHz class-J PA with the same transistor size and bias condition as the class-J2 PA is also fabricated. The output power and PAE of the reference class-J PA are 11.4 dBm and 40.6%, respectively, which are in agreement with theoretical predictions.

Filtering Power Amplifier With Wide Bandwidth Using Discriminating Coupling

This paper presents a filtering power amplifier (PA) with wide bandwidth. A bandpass filter (BPF) using discriminating coupling is first proposed to be utilized as the output matching network (OMN) of PA. Discriminating coupling means that the fundamental and the harmonics of the proposed structure have different coupling coefficients. Thus, the input impedances of the fundamental, second and third harmonics could meet the requirements of the extended continuous mode theory, respectively. Also, good frequency selectivity is obtained. The working principle of discriminating coupling, the filter synthesis theory and the equivalent circuit are utilized to guide the design of the filtering PA. To demonstrate the proposed structure, a compact filtering PA operating at 1.8 GHz is designed. The measured results exhibit good frequency selectivity and high power added efficiency (PAE). More importantly, comparing to the previous filtering power amplifiers (PAs) with good frequency selectivity, the proposed design possesses wide bandwidth of 31.1% with PAE higher than 60%.

A 3.5-GHz Class-F Power Amplifier with Current-Reused Topology in 0.13-μm CMOS for 5G Application

In this paper, a 3.5-GHz class-F Power Amplifier with current-reused topology in 0.13-[Formula: see text]m CMOS for 5G application is presented. This proposed circuit has a two-stage structure by a current-reused topology driving to improve gain and the stability of PA. An output matching network is constructed by an open-circuited third harmonic resonator that can integrate the current and voltage waveform in the time domain adopted to improve the output power and reduce power consumption. The simulation results show that the proposed PA provides a 13[Formula: see text]dBm output power with a PAE of 50.5% and a small signal gain of 32.5[Formula: see text]dB that is higher than reported for a two-stage design in CMOS at the 3.5-GHz frequency, while the minimum output return loss ([Formula: see text]) is [Formula: see text]14.4[Formula: see text]dB with a minimum value of [Formula: see text]24.67[Formula: see text]dB. Many experiments are carried out to prove that the proposed PA has higher gain and higher efficiency compared to the traditional class-F power amplifier and is suitable for 5G short-range applications. Finally, the layout occupies a compact chip area of [Formula: see text][Formula: see text]mm2, including testing pads.

A Triple-Band CMOS Power Amplifier Using Multi-Band and Switchable Matching Network for Wireless Mobile

A triple-band CMOS power amplifier (PA) is presented. We propose a design methodology using an input matching network to support triple-band operation at 0.9, 1.8, and 2.4 GHz. We also propose an output matching network for the triple-band operation. Given that 1.8 and 2.4 GHz are the harmonic components when the PA is operating at 0.9 GHz, we design the output matching network to be switchable to suppress the harmonic components at the operating frequency. Using this switchable network, we obtain an optimum power matching point for each of the three operating frequencies. To verify the feasibility of the proposed structure, we designed a PA using a 180-nm RFCMOS process. It was measured using a wideband code division multiple access (WCDMA), Long-Term Evolution (LTE) at a 10/20-MHz bandwidth and wireless local area network (WLAN) 802.11n applications. The measured output power was 27.2/26.6 dBm, and the power-added efficiency (PAE) was 22.9%/30.6% under an adjacent channel leakage ratio (ACLR) of -33 dBc at 0.95/1.8 GHz, respectively, with a WCDMA modulation signal. In the case of an LTE modulation signal, the measured output power was 25.1/23.5 dBm, and the PAE was 27.7%/23.6% under an ACLR of −30 dBc for a 10/20-MHz bandwidth, respectively, at 1.8 GHz. The measured output power was 21 dBm, and the PAE was 20% under an error vector magnitude (EVM) of 3.98% at 2.4 GHz for a WLAN modulation signal. Based on the measured results, we successfully verified the feasibility of the proposed PA.

Single Stage 180nm CMOS Low Noise Amplifier Topologies and Optimization Algorithms for S Band Frequency

Low Noise Amplifier (LNA) plays an important role in radio receivers. It mainly determines the system noise and intermodulation behavior of overall receiver. LNA design is more challenging as it requires high gain, low noise figure, good input and output matching and unconditional stability. Further, designing a Low noise Amplifier requires active device selection, amplifier topology, optimization algorithms for superlative results. Hence this paper presents performance analysis of CMOS LNA based on different topologies and optimization algorithms for 180nm RF CMOS design in S band frequency. Here the best results, various limitations in each topology are reviewed and required specifications are determined in each designing. Further this best topology is used for designing LNA circuit which could be used in Indian Regional Navigation Satellite System (IRNSS) applications in dual band frequency.

T85MIR137 POLYGENIC RISK FOR SCHIZOPHRENIA AND ITS ROLE IN LATERAL VENTRICLES AND CORPUS CALLOSUM VOLUME

This paper presents a twelve-mode 130 nm CMOS power amplifier with reconfigurable output matching network (OMN) and supply voltage selection. To select operation modes, nine inputs enable or disable individually a set of power cells in the power stage and capacitors in the OMN. The gain stage is a cascode structure while the power stage is composed of three differently sized parallel cascode power cells with a voltage supply ranging from 1.1 V to 1.8 V. The OMN is composed of two reconfigurable capacitor banks and a fixed inductor. Each bank is composed of three capacitance cells. When a different combination of power cells is enabled, the OMN is altered to match impedances and so improve efficiency. The low-power mode achieves an output 1 dB compression point (OCP1dB) of 10.1 dBm, a DC power (PDC) consumption of 94.7 mW, and 10.6% power added efficiency (PAE) at OCP1dB. The high-power mode achieves an OCP1dB of 18.22 dBm, 341.4 mW PDC and 19.4% PAE at OCP1dB. Employing IEEE 802.11n, IEEE 802.11ax and LTE signals for each mode, digital channel simulations were performed to determine the maximum output power in compliance with the respective Error Vector Magnitude and Adjacent Channel Power Ratio.

A broadband 23.1 ∼ 27.2 GHz doherty power amplifier with peak output power of 24.3 dBm

Purpose This paper aims to implement a new high output power fully integrated 23.1 to 27.2 GHz gallium arsenide heterojunction bipolar transistor power amplifier (PA) to meet the stringent linearity requirements of LTE systems. Design/methodology/approach The direct input power dividing technique is used on the chip. Broadband input and output matching techniques are used for broadband Doherty operation. Findings The PA achieves a small-signal gain of 22.8 dB at 25.1 GHz and a saturated output power of 24.3 dBm at 25.1 GHz with a maximum power added efficiency of 31.7%. The PA occupies 1.56 mm2 (including pads) and consumes a maximum current of 79.91 mA from a 9 V supply. Originality/value In this paper, the author proposed a novel direct input dividing technique with broadband matching circuits using a low Q output matching technique, and demonstrated a fully-integrated Doherty PA across frequencies of 23.1∼27.2 GHz for long term evolution-license auxiliary access (LTE-LAA) handset applications.

Remote Sensing Image Matching Algorithm for Coastal Zone Based on Local Features

Li, M. and Xie, W., 2019. Remote sensing image matching algorithm for coastal zone based on local features. In: Guido-Aldana, P.A. and Mulahasan, S. (eds.), Advances in Water Resources and Exploration. Journal of Coastal Research, Special Issue No. 93, pp. 723–728. Coconut Creek (Florida), ISSN 0749-0208.In order to improve the high resolution digital imaging ability of coastal remote sensing image, a pixel spatial fusion feature matching method based on local feature adaptive feature matching is proposed. The edge profile feature detection and pixel reconstruction model of coastal remote sensing image is constructed, and the multi-level feature decomposition and pixel region profile feature detection of coastal remote sensing image are carried out. The optimal high spatial resolution feature of coastal zone remote sensing image is extracted, and the high spatial edge profile feature extraction and block segmentation of coastal zone remote sensing image are carried out by using similarity information fusion and image region reconstruction methods. The target block matching and overlapping region high resolution reconstruction of coastal zone remote sensing image are carried out based on approximate sparse representation method, and the pixel spatial fusion feature matching of coastal zone remote sensing image is carried out under the constraint of high resolution. The simulation results show that the fusion degree of pixel spatial fusion feature matching of coastal remote sensing image is high, the reconstruction quality of image is good, the peak signal-to-noise ratio of output is high, the matching output quality of coastal remote sensing image is good, and it has good image resolution and detection ability.

A CMOS power amplifier with reconfigurable power cells and matching network for 2.4 GHz wireless communications

This paper presents a twelve-mode 130 nm CMOS power amplifier with reconfigurable output matching network (OMN) and supply voltage selection. To select operation modes, nine inputs enable or disable individually a set of power cells in the power stage and capacitors in the OMN. The gain stage is a cascode structure while the power stage is composed of three differently sized parallel cascode power cells with a voltage supply ranging from 1.1 V to 1.8 V. The OMN is composed of two reconfigurable capacitor banks and a fixed inductor. Each bank is composed of three capacitance cells. When a different combination of power cells is enabled, the OMN is altered to match impedances and so improve efficiency. The low-power mode achieves an output 1 dB compression point (OCP1dB) of 10.1 dBm, a DC power (PDC) consumption of 94.7 mW, and 10.6% power added efficiency (PAE) at OCP1dB. The high-power mode achieves an OCP1dB of 18.22 dBm, 341.4 mW PDC and 19.4% PAE at OCP1dB. Employing IEEE 802.11n, IEEE 802.11ax and LTE signals for each mode, digital channel simulations were performed to determine the maximum output power in compliance with the respective Error Vector Magnitude and Adjacent Channel Power Ratio.

Broadband Doherty power amplifier with improved band‐pass auxiliary network

In this article, a Doherty power amplifier (DPA) with improved band-pass auxiliary impedance inverter is proposed for broadband operation. As a wideband DPA solution, the output matching networks of main and auxiliary devices are designed to achieve proper impedance matching at back-off and peak power by employing a two-point matching technique without the λ/4 impedance transformer. It is found that the modified band-pass network has broader bandwidth feature and is compact in form from the comparison with some different topologies of matching networks. So, it is more suitable to be the auxiliary transformer to achieve the broadband configuration of DPA. For validation purpose, a Doherty power amplifier based on two commercially available gallium nitride HEMT (Cree CGH 40010F) devices was designed, fabricated, and measured. Under the drive of continuous wave (CW) signal, the measurement results show that the DPA has a 6-dB back-off efficiency of 35% to 48% and a saturated efficiency of 44% to 64% within the frequency band from 1.50 GHz to 2.35 GHz, which is about 44% fractional bandwidth.

Wideband out-of-phase power divider using Klopfenstein tapered line transformers

A novel wideband out-of-phase power divider based on Klopfenstein tapered line is proposed for the first time. By using double-sided parallel-strip line (DSPSL) with inserted conductor plane as virtual ground, frequency-independent phase difference can be achieved with antisymmetric output structures. Odd-/even-mode analysis shows that the introduced Klopfenstein tapered line can expand bandwidth greatly, and additional eight pairs of isolation resistors are added to realize high output matching and isolation. For verification, this presented power divider is fabricated and measured. The simulation and measurement show that this structure can achieve a wide frequency range from 0.5 GHz to 7.3 GHz, within which the S-parameters (S11, S22, S32) are all better than −10 dB, and the phase imbalance is less than 7°.