Address Mapping Research Articles

A soft computing model for mapping incomplete/approximate postal addresses to mail delivery points

Mapping of postal address to a mail delivery point is a very important task that affects the efficiency of postal service. This task is very complex in the countries such as India, where postal addresses are not structured. Further most of the times the destination addresses in such countries are incomplete, approximate and erroneous which adds to the complexity of mapping postal address to delivery point. Automation of this aspect of the postal service is a challenge. This paper presents a soft computing model to map the postal address to mail delivery point. Firstly machine readable postal address is processed to identify the address components using a novel fuzzy symbolic similarity analysis, and further these labeled components are organized as a symbolic postal address object. This postal address object is further processed using the newly devised fuzzy symbolic methodology for mapping the address to mail delivery point. Symbolic knowledge bases for postal address component labeling and mail delivery point mapping are devised. Fuzzy symbolic similarity measures are formulated once for address component labeling and the second time for mapping the entire address to a mail delivery point. In sequel to similarity computations, which are viewed as fuzzy membership values, an expert system comprising of α-cut de-fuzzification is proposed to evaluate the confidence factors, while inferencing the validity of address component labels and mail delivery points. The system is tested exhaustively and an efficiency of 94% is obtained in address component identification and about 86% in mail delivery point mapping, while working on an Indian postal data base of about 500 addresses.

Configurable Flash-Memory Management: Performance versus Overheads

Flash memory is widely adopted in various consumer products for information storage, especially for embedded systems. With strong demands on product designs for overhead control and performance requirements, vendors must have an effective design for the mapping of logical block addresses (LBA's) and physical addresses of data over flash memory. This paper targets such an essential issue by proposing a configurable mapping method that could trade the main-memory overhead with the system performance under the best needs of vendors. A series of experiments is conducted to provide insights on different configurations and the proposed method, compared to existing implementations.

VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder

A high-speed VLSI design of an area-efficient JPEG2000 encoder is given. Recursive multilevel 2D discrete wavelet transform (DWT) architecture with dual buffers is proposed to reduce the wavelet coefficients memory to 1/4 tile size, prerate allocation is used to reduce the compressed code memory to 3/4 tile size. A highly pipelined and parallelism implementation of line-based 1-level DWT is proposed using two line-buffers in 5/3 wavelet type and its input speed is up to 2 samples/cycle; code block based address mapping in access wavelet coefficients memory, concurrent state variables generation and multiple parallel and pipeline coding methods are used in the bit plane encoder (BPE) which encodes on average at 40.5 M samples/s at 100 MHz with no memory used; the conditional two-symbol pipeline arithmetic encoder (AE) encodes at 1.3 symbols/cycle. Parallel units in BPE and buffer control between BPE and AE are optimally implemented with low cost without performance loss. Byte representation of rate-distortion slope used reaches a near optimal implementation of post-coding rate distortion in Tier2 with low cost. The compressed file generated by the encoder is fully compatible with ISO/IEC FCD15444-1. The encoder is verified on field-programmable gate array platform with a direct interface to digital video input with tile size 256 times 256 and code block size 32 times 16. The resulting input sampling rate is up to 58 M samples/s when Tier1 operates at 100 MHz. Difference of the peak signal-to-noise ratio of images compressed by our encoder and JasPer is less than 0.2 dB when the compression ratio is greater than 1 bps. Equivalent NAND2 gates synthesized are 90.6 K and on-chip RAM size is 626.75 kb. Unlike other designs the proposed design of JPEG2000 encoder has high compression quality as well as high speed and area-efficiency.

TARP: Ticket-based address resolution protocol

IP networks fundamentally rely on the Address Resolution Protocol (ARP) for proper operation. Unfortunately, vulnerabilities in ARP enable a raft of Internet Protocol (IP)-based impersonation, man-in-the-middle, or Denial of Service (DoS) attacks. Proposed countermeasures to these vulnerabilities have yet to simultaneously address backward compatibility and cost requirements. This paper introduces the Ticket-based Address Resolution Protocol (TARP). TARP implements security by distributing centrally issued secure IP/Medium Access Control (MAC) address mapping attestations through existing ARP messages. We detail TARP and its implementation within the Linux operating system. We also detail the integration of TARP with the Dynamic Host Configuration Protocol (DHCP) for dynamic ticket distribution. Our experimental analysis shows that TARP improves the costs of implementing ARP security by as much as two orders of magnitude over existing protocols. We conclude by exploring a range of operational issues associated with deploying and administering ARP security.

Defect and Transient Fault-Tolerant System Design for Hybrid CMOS/Nanodevice Digital Memories

Targeting on the future fault-prone hybrid CMOS/nanodevice digital memories, this paper presents two fault-tolerance design approaches that integrally address the tolerance for defects and transient faults. These two approaches share several key features, including the use of a group of Bose-Chaudhuri-Hocquenghem (BCH) codes for both defect tolerance and transient fault tolerance, and integration of BCH code selection and dynamic logical-to-physical address mapping. The first approach is straightforward and easy to implement but suffers from a rapid drop of achievable storage capacity as defect densities and/or transient fault rates increase, while the second approach can achieve much higher storage capacity under high defect densities and/or transient fault rates at the cost of higher implementation complexity and longer memory access latency. Based on extensive computer simulations and BCH decoder circuit design, we have demonstrated the effectiveness of the presented approaches under a wide range of defect densities and transient fault rates, while taking into account of the fault-tolerance storage overhead and BCH decoder implementation cost in CMOS domain

An Enhanced Memory Address Mapping Scheme for Improved Memory Access Performance of 2-D DWT Processing Systems

The implementation of the memory for storing image and transform coefficients in 2-D DWT processing systems using the more cost-effective external memory module such as DDR DRAM is shown to suffer from effective memory bandwidth which is significantly lower than the memory system peak bandwidth if the conventional direct logical-to-physical memory address mapping is adopted. The low effective memory bandwidth is caused by the high level of memory overhead cycle occurrence which is in turn is closely related to the logical memory access patterns of 2-D DWT processes. The problem becomes even more severe for the 2-D DWT processing of video. An analysis on the logical memory access patterns of multi-level 2-D DWT is carried out and an enhanced logical-to-physical memory mapping scheme which minimizes the occurrence of memory overhead cycles is proposed. The proposed scheme is simulated and its performance in terms of effective memory access bandwidth is evaluated and compared with the conventional direct mapping scheme.

Large-capacity high-throughput low-cost pipelined CAM using pipelined CTAM

A novel approach toward realizing a large capacity high-throughput pipelined content addressable memory (CAM) or associative memory (AM) at low cost has been described. It employs only commercial random access memory (RAM) along with a simple binary search pipeline (BSPL). In order to search a (2/sup n/-1)-word search key field (SKF) storage RAM, the BSPL employs n identical and simple binary search processing elements, each having its local copy of the SKF storage RAM (SKFSR). The SKFSR stores, in an ordered manner, the SKFs of all the words in the CAM, whereas a data field storage RAM (DFSR) stores the unordered CAM data words. The n-times replicated SKFSR, along with the n-processor BSPL, functions as a simple n-stage pipelined content-to-address memory (CTAM). The CTAM, a new kind of memory that performs the inverse function of a RAM, serves as the first and the most important stage in the proposed 3-stage pipelined CAM architecture. In response to the stream of input query words (search keys) fed to the pipelined CAM, the pipelined CTAM first produces the corresponding stream of SKFSR addresses where the query words reside. These SKFSR addresses corresponding to the queries are next mapped back by the second stage, namely, the address mapping RAM, to their original addresses in the CAM, i.e., in the DFSR, which had been altered due to data ordering in the SKFSR. Now, the third stage of the pipelined CAM, namely, the DFSR, is read out at the mapped, i.e., the original CAM addresses, to obtain the desired stream of responses from the CAM. An augmented version of the pipelined CTAM has been designed to handle the presence of duplicate search keys in the CAM. A few illustrative examples of querying a simple database stored in the CAM have been included. The proposed pipelined CAM has a modular and highly scalable architecture. Its throughput rate, which is independent of the CAM size, is a little less than the RAM access rate and its latency is a little more than (n+2) times the RAM access time.

RESIZABLE TRANSLATION STORAGE BUFFERS

A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement.

Hardware Implementation of Fuzzy PID Controllers

For traditional hardware implementation of fuzzy PID controllers, it is large at computation and bad in real-time performance, so, a kind of PID control algorithm, whose gain parameters could be tuned by their fuzzy system, was selected as studying example for a novel idea of hardware implementation. In this paper, authors presented hardware network of memory address mapping to implement fuzzy PID control algorithm, and designed the corresponding hardware system. The idea actually realizes fusion of hardware and intelligent algorithm. The implementation effectively simplified hardware circuits, the whole controller is very simple without CPU. Meanwhile, it is very easy to use, only connecting the sensor/transducer, the driver and the actuator is OK. The controller is very rapid in response, it need only two A/D conversion periods for outputting a required control signal. So the implementation could meet real-time performance effectively.

Minimizing the Directory Size for Large-Scale Shared-Memory Multiprocessors

Directory-based cache coherence schemes are commonly used in large-scale shared-memory multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed using physical address mapping on directories to significantly reduce directory size needed. This approach allows the size of directory to grow as O(cnlog2n) as in optimal pointer-based directory schemes [11], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Performance aspects of the proposed scheme are studied in detail using simulation.

An address mapping approach for test data generation of dynamic linked structures

Software testing is an important technique to assure the correctness of the software. One of the essential prerequisite tasks of software testing is test data generation. This paper proposes an approach to generate test data specifically for dynamic pointer structures. In our context, a pointer is considered and handled as a location in memory, represented by a dynamic linear array that expands and shrinks during execution. As such, pointer test data can be directly generated from this linear array. The proposed technique can also support any dynamic structures, as well as homogeneous and heterogeneous recursive structures.

Proposal and implementation of IPv4–IPv6 bidirectional communication system

AbstractCommunication between an IPv6 host and an IPv4 host requires a name server that makes a mapping between an IPv4 address and an IPv6 address, and a translator that performs IP packet conversion. In this paper, we propose an IPv4–IPv6 bidirectional communication system, implement our proposed method, and present the results of performance evaluation. Our system can provide IPv4 hosts with connectivity to more IPv6 hosts in spite of pooling fewer IPv4 addresses. It is realized by adding a source IPv4 address and a port number to an address mapping with cooperation between a name server and a translator. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 1, 87(12): 49–59, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecja.10203

An Associative Architecture of CMAC for Mobile Robot Motion Control

A new design scheme for the Cerebellar Model Articular Controller (CMAC) is presented in this article. The controller is designed with a content addressable memory (CAM) that replaces the function of the hash-coding method, which is adopted by the traditional CMAC and consumes much computation power in memory space mapping. Therefore, address mapping in the proposed CMAC is different from the hash-coding method. The CAM, which is capable of fast comparison, can immediately determine in parallel if there is any identical data in memory as the input data to be compared. If a match does not occur, the activated address is then stored in a vacant cell of the CAM indexed by a circular incremental pointer. Memory collision can be avoided unless the memory is fully occupied. In this way, the memory utilization rate can be improved to 100%, which is difficult to achieve using the conventional schemes. Meanwhile, control noise can be largely suppressed. In content addressing, the associated mask function, which is triggered when the CAM is full, can decrease the probability of collision and improve control performance. Simulation results of function approximation and truck backer-upper control indicate that the proposed CMAC is clearly superior to the conventional CMACs.

A performance study of robust load sharing strategies for distributed heterogeneous Web server systems

Replication of information across multiple servers is becoming a common approach to support popular Web sites. A distributed architecture with some mechanisms to assign client requests to Web servers is more scalable than any centralized or mirrored architecture. In this paper, we consider distributed systems in which the Authoritative Domain Name Server (ADNS) of the Web site takes the request dispatcher role by mapping the URL hostname into the IP address of a visible node, that is, a Web server or a Web cluster interface. This architecture can support local and geographical distribution of the Web servers. However, the ADNS controls only a very small fraction of the requests reaching the Web site because the address mapping is not requested for each client access. Indeed, to reduce Internet traffic, address resolution is cached at various name servers for a time-to-live (TTL) period. This opens an entirely new set of problems that traditional centralized schedulers of parallel/distributed systems do not have to face. The heterogeneity assumption on Web node capacity, which is much more likely in practice, increases the order of complexity of the request assignment problem and severely affects the applicability and performance of the existing load sharing algorithms. We propose new assignment strategies, namely adaptive TTL schemes, which tailor the TTL value for each address mapping instead of using a fixed value for all mapping requests. The adaptive TTL schemes are able to address both the nonuniformity of client requests and the heterogeneous capacity of Web server nodes. Extensive simulations show that the proposed algorithms are very effective in avoiding node overload, even for high levels of heterogeneity and limited ADNS control.

Hidden double data transfer scheme for MDL design

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 µm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory.

Two-dimensional shared memory multicast ATM switching architecture

Currently, the advances in the communication field are tending towards the Broadband Integrated Services Digital Network (BISDN) based on the Asynchronous Transfer Mode (ATM). Although numerous studies have been carried out in point-to-point switching systems, the point-to-multipoint switching system has gradually gained significance in recent years. To meet the requirement of the multicast service, we proposed a high-performance multicast switching system. There are easy ways to setup and release a multicast call. Only one copy of the address mapping information should be maintained in the system. The multicast cell overflow condition is trivially solved by our proposed switching architecture. We provide an overlay scheme to reduce delay needed in the multicast cell copying process. Finally, we afford a simulation result to evaluate the performance of the proposed multicast switching system.

Extension of classical IP over ATM to support QoS of the application level

After the introduction of the basic concepts of classical IP over ATM (CLIP), this paper presents an extension to this standard as well as a full analysis of the technical viability of the extension proposal. One of the major drawbacks of CLIP is the co-existence of IP and ATM without quality of service (QoS) support. By extending the functionality of CLIP and redefining the mapping of IP and ATM addresses, QoS can be brought to IP-based applications without requiring any specific definition or implementation changes at the IP layer or above. QACLIP (QoS for applications using CLIP), the newly defined extension, allows applications to request specific QoS for their data transfer use.

U-cache: A cost-effective solution to the virtual cache synonym problem

This paper proposes a cost-effective solution to the virtual cache synonym problem. In the proposed solution, a minimal hardware addition guarantees correct handling of the synonym problem whereas a simple modification to the virtual-to-physical address mapping in the operating system optimizes the performance. The key to the proposed solution is a small, physically-indexed cache called a U-cache. The U-cache maintains the reverse translation information of cache blocks that belong to unaligned virtual pages, where unaligned means that the lower bits of the virtual page number that are used to index the virtual cache do not match those of the corresponding physical page number. The biggest advantage of the U-cache approach is that it leaves room for software optimization in the form of mapping alignment. Performance evaluation based on memory reference traces from a real system shows that the U-cache, with only a few entries, performs almost as well as (in some cases outperforms) a fully-configured hardware-based solution when more than 95% of mappings are aligned.

High-level programming of massively parallel computers based on shared virtual memory

Highly parallel machines needed to solve compute-intensive scientific applications are based on the distribution of physical memory across the compute nodes. The drawback of such systems is the necessity to write applications in the message passing programming model. Therefore, a lot of research is going on in higher-level programming models and supportive hardware, operating system techniques, languages. The research direction outlined in this article is based on shared virtual memory systems, i.e., scalable parallel systems with a global address space which support an adaptive mapping of global addresses to physical memories. We introduce programming concepts and program optimizations for SVM systems in the context of the SVM-Fortran programming environment which is based on a shared virtual memory system implemented on Intel Paragon. The performance results for real applications proved that this environment enables users to obtain a similar or better performance than by programming in HPF.

Hardware implementation of CMAC neural network with reduced storage requirement

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100%. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.