Hidden double data transfer scheme for MDL design

Abstract

A high-speed DRAM data transfer scheme between DRAM and logic parts in merged DRAM logic (MDL) designs is proposed with logically divided DRAM row address mapping. The proposed scheme results in a 20% faster write access and 40% faster read access. It can be used as a general design framework to maximise DRAM access speed in various MDL designs. A test chip has been fabricated by 0.16 µm DRAM technology, and the scheme has been verified in the design of a DRAM L2 cache memory.