RESIZABLE TRANSLATION STORAGE BUFFERS

Abstract

A translation lookaside buffer (TLB) is a high-speed associative cache of recently used virtual-to-physical address translations. The operating system can deal with a TLB miss through software trap handling. A possible technique for such software trap handling uses translation storage buffers (TSBs). A TSB is an operating system data structure that caches the most recent address translations. On a TLB miss, the TLB trap handler searches the TSB for the missing address translation. If the search generates a hit, the address mapping is added to the TLB. In current implementations, TSBs are organized in a variety of ways: a global TSB for all CPUs within the system, a per-processor TSB, or a per-process TSB. All of the aforementioned techniques have various limitations that will be addressed in this paper. In this work, we propose a new framework for TSBs generation and allocation. In the proposed approach, a policy of resizing and dynamically allocating TSBs for the different processes is used. This dynamic policy allows the system to adopt to different workloads while achieving a low TSB context invalidation overhead. In addition, with the ability to assign a separate TSB to each process, thrashing is practically eliminated. Implementation and experimental results of the proposed scheme are reported. Comparisons against existing implementations confirmed the expected performance enhancement.