Magnetic Random Access Memory Research Articles

Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau–Lifshitz–Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%–87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.

Atomistic Investigation of Interface Edge Defect in CoFeB/MgO Ferromagnetic Nano-Dots

The spin transfer torque (STT) based magnetic random access memory (MRAM) device has been seen as the next general storage device which can realize non-volatile storage and in-memory computing. However, the shape defect that comes from the fabrication process will influence the performance of the MRAM device. In this work, the relationship between the critical current and switching time and the interface edge defect in a CoFeB MRAM is studied by the atomistic spin model. The atomistic simulations that the effect of the interface edge defect depends on the thickness of the magnetic layer, the operating temperature and the driven current density. Our finding should also benefit the control of the fabrication process of the STT-based technologies.

Growth temperature-controlled Gilbert damping and anisotropies in PLD grown epitaxial Co2FeSi Heusler alloy thin film

The utilization of spin rather than charge as a functional aspect in the electronic devices will result in an energy-efficient, thermally stable, and fast operation. Cobalt-based Heusler alloy Co2FeSi (CFS) offers excellent possibilities due to its high curie temperature, large spin polarization, and low Gilbert damping (α). Small damping makes the alloy fascinating for spin transfer torque magnetoresistive random-access memory (STT-MRAM) devices where a low α causes a low value of switching current. The present investigation explored the effect of deposition temperature on the chemical, structural and magnetic properties of the pulsed laser deposition grown single-crystal CFS film of thickness 50 nm on a lattice-matched (001) MgO substrate. The XRD data suggest that Co site atomic ordering and overall film crystallinity improved with temperature, resulting in a minimal value of α obtained from ferromagnetic resonance (FMR) experiment in the film grown at 600°C. The azimuthal angular variation (φ) of FMR field data gives a fourfold anisotropy pattern that confirms the single-crystal CFS film epitaxially grown on the MgO substrate. Two in-plane anisotropies, namely cubic (four-fold) and uniaxial, were obtained in all the samples. This investigation is crucial in the fabrication of fast spintronics based memory and processing devices.

Field-free switching model of spin–orbit torque (SOT)-MTJ device with thermal effect based on voltage-controlled magnetic anisotropy (VCMA)

Electrically driven magnetization switch has attracted much attention in the new spintronic memory, especially for spin–orbit torque (SOT)-based magnetic random access memory (MRAM). However, the published models are facing limitations with the continuous shrinkage of the feature size down to nanoscale. Also, the thermal effect caused by switching operation is non-negligible. Therefore, an effective model is needed to represent the switching dynamic of the device concerning the influences of the nanoscale and the thermal effect. In the paper, a compact model of three-terminal SOT-driven switching is established. The influence of the voltage-controlled magnetic anisotropy (VCMA) and spin transfer torque (STT) effect induced by bias voltage on the field-free SOT-driven switching is considered by numerically solving the LLG equations. Furthermore, a 3D model of the SOT-MTJ device is established by finite element method to trace the thermoelectric behavior inside the device. The thermoelectric behavior is integrated into the compact model to show the influence of the temperature on the switching behavior, highlighting the importance of the thermal effect for the realistic modelling of SOT-driven switching. Finally, a novel voltage pulse scheme is proposed, which can effectively shorten the switching time and improve the reliability of the device. The established model could provide strategies and guidelines for next-generation memory design and application.

Low magnetic damping in an ultrathin CoFeB layer deposited on a 300 mm diameter wafer at cryogenic temperature

We deposited an ultrathin CoFeB(1.1 nm) layer, which functions as a storage layer of MgO-based magnetic tunnel junctions for spin-transfer-torque (STT) magnetoresistive random-access memory (MRAM), on ϕ300 mm wafers at 100 K and investigated its effect on the magnetization dynamics of CoFeB. We observed clear reductions in both the inhomogeneous linewidth and total magnetic damping parameter for the CoFeB layer deposited at 100 K compared to those deposited at 300 K through the improvement in the interfacial quality. The results show that deposition at cryogenic temperatures is an effective manufacturing process for high-quality magnetic thin films with low magnetic damping.

Time-domain computing for Boolean logic using STT-MRAM

With the development of artificial intelligence, the separation of memory and processor in the traditional von-Neumann architecture has led to the bottleneck of data transmission hindering the development of energy efficient computing. The computing-in-memory (CIM) paradigm is expected to solve the problems of memory wall and power wall. In this work, we propose a time-domain (TD) computing scheme based on the spin transfer torque magnetic random access memory (STT-MRAM). Basic Boolean logic operations, such as AND/OR/Full-adder (FA), are implemented through converting the bit-line voltage to time delay and time-to-digital converter (TDC). The proposal is simulated using the 28 nm CMOS process and 40 nm MTJ compact model. Monte-Carlo simulations show that 94.2% to 100% computation accuracy can be obtained and the delay of AND/OR and FA is 2.5 ns and 3.5 ns. The energy consumption of AND/OR and FA achieve 59.43 fJ and 97.56 fJ, respectively.

Design of a Compact Spin-Orbit-Torque-Based Ternary Content Addressable Memory

This article presents the design of a novel and compact spin-orbit torque (SOT)-based ternary content addressable memory (TCAM). Experimentally validated/calibrated micromagnetic and macrospin simulations have been used to quantify various tradeoffs regarding the write operation, such as write energy, error rate, and retention time. SPICE simulations incorporating various sources of variability are used to evaluate search operations, optimize the proposed novel TCAM cell based on SOT magnetic random access memory (SOT-MRAM), and benchmark it against static random access memory (SRAM)- and FeFET-based TCAMs. We show low search error rates (SERs) (< 10−4) while considering various sources of variability for four transistors- and two magnetic tunnel junctions (MTJs)-based TCAM array.

Parallel-Prefix Adder in Spin-Orbit Torque Magnetic RAM for High Bit-Width Non-Volatile Computation

Recently, many computing-in-memory (CIM) systems based on non-volatile devices have been implemented well. However, they perform poorly in high bit-width processes due to device access latency and energy cost. In this brief, we present an in memory fully non-volatile parallel-prefix adder(PPA) based on CIM system for 2T1MTJ spin-orbit torque magnetic random access memory(SOT MRAM). Unlike traditional CMOS circuits, CIM prefers uniform logic gates(only AND or OR gates at each logic level). Thus, to calculate the output of each logic level, traditional AND/OR logic is substituted with MAJORITY/NOT logic. We also propose an optimized logical mapping strategy that requires one write operation instead of continuous write operations at each write-back stage, which maximizes the performance benefits of the PPA.

Perspectives on field-free spin–orbit torque devices for memory and computing applications

The emergence of embedded magnetic random-access memory (MRAM) and its integration in mainstream semiconductor manufacturing technology have created an unprecedented opportunity for engineering computing systems with improved performance, energy efficiency, lower cost, and unconventional computing capabilities. While the initial interest in the existing generation of MRAM—which is based on the spin-transfer torque (STT) effect in ferromagnetic tunnel junctions—was driven by its nonvolatile data retention and lower cost of integration compared to embedded Flash (eFlash), the focus of MRAM research and development efforts is increasingly shifting toward alternative write mechanisms (beyond STT) and new materials (beyond ferromagnets) in recent years. This has been driven by the need for better speed vs density and speed vs endurance trade-offs to make MRAM applicable to a wider range of memory markets, as well as to utilize the potential of MRAM in various unconventional computing architectures that utilize the physics of nanoscale magnets. In this Perspective, we offer an overview of spin–orbit torque (SOT) as one of these beyond-STT write mechanisms for the MRAM devices. We discuss, specifically, the progress in developing SOT-MRAM devices with perpendicular magnetization. Starting from basic symmetry considerations, we discuss the requirement for an in-plane bias magnetic field which has hindered progress in developing practical SOT-MRAM devices. We then discuss several approaches based on structural, magnetic, and chiral symmetry-breaking that have been explored to overcome this limitation and realize bias-field-free SOT-MRAM devices with perpendicular magnetization. We also review the corresponding material- and device-level challenges in each case. We then present a perspective of the potential of these devices for computing and security applications beyond their use in the conventional memory hierarchy.

Interfacial Engineering Strategies for Efficient Spin–Orbit Torque Devices with Pt Alloys

To make spin–orbit torque magnetic random-access memories (SOT-MRAMs) become competitive enough to replace the contemporary memory architecture, it is of great importance to utilize conductive SOT materials that possess large damping-like spin–orbit torque (DL-SOT) efficiencies and back-end-of-line (BEOL) compatibility. In this work, we report a BEOL-compatible CoFeB/MgO-based heterostructure with the Pt–Cr alloy as the spin current source (SCS) and inserted a Pt/Co/Pt composite layer to achieve texture decoupling and ferromagnetic coupling. A thermally robust perpendicular magnetic anisotropy (PMA) of the hybrid heterostructure can be retained after annealing at 400 °C for 1 h, while maintaining large DL-SOT efficiencies of the annealed Pt–Cr alloys (ξDL ∼ 0.34 for Pt0.70Cr0.30). Additionally, by optimizing the current distribution with a resistive Pt spacer layer, it is possible to simultaneously enhance the current-to-effective field conversion ratio (Hzeff/I) and retain the apparent ξDL (ξDL ∼ 0.37 for Pt0.79Cr0.21). Moreover, the critical switching current density can be reduced from JcPt ∼ 2.0 × 107 A·cm–2 for Pt to JcPt0.70Cr0.30 ∼ 4.9 × 106 A·cm–2 for Pt0.70Cr0.30 without tampering the thermal stability of the annealed heterostructure. These interfacial engineering strategies provide directions to integrate Pt-based SCSs with large ξDL into a BEOL-compatible platform for future SOT-MRAM devices with PMA.

A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router

Network-on-chip (NoC) offers a scalable and flexible communication infrastructure for many-cores systems. Buffers in router is used for fine-grain flow control and Quality of Service (QoS), yet it is the major contributor of area and power consumption. In this paper, we propose a hybrid buffer design with SRAM and Spin-Torque Transfer Magnetic RAM (STT-RAM) for NoC router leveraging a novel architecture combined Virtual Channel (VC) and Virtual Output Queuing (VOQ) to store congested and uncongested flow separately. Experiments demonstrates that the proposed scheme can achieve 11.8% network performance improvement and 32.9% power saving with only 8.2% area overhead degradation compared to conventional SRAM based buffer design.

Switching current reduction in magnetoresistive random access memories

We present an approach for minimizing the critical current for the magnetization switching in magnetic tunnel junctions by optimizing the spatial distribution of the current density. We show that such a minimization is possible because critical current is determined by the condition of making one of the magnetization eigenstates grow in time. The excitation of the eigenstates is enhanced when the spatial distributions of the eigenstates and current density overlap. Critical current can be viewed as a functional of the current density spatial distribution and it can be minimized by optimizing this distribution. Such an optimization results in a major reduction of the critical current and increase of the switching efficiency, viz. the ratio between the energy barrier and critical current. The minimized critical current increases approximately linearly with the magnetic tunnel junction size, which is much slower than critical current for the case of a uniform current density. The optimized efficiency can be approximately a constant with respect to the magnetic tunnel junction size, which is much higher than the efficiency for the uniform current density. Additional optimization can be achieved by spatially modulating the material parameters, e.g., the saturation magnetization. The presented approach and obtained scaling of the critical current and efficiency offers opportunities for the magnetic tunnel junction optimization.

Voltage-gated spin-orbit torque switching in IrMn-based perpendicular magnetic tunnel junctions

In this work, IrMn-based perpendicular magnetic tunnel junctions (MTJs) are investigated. By inserting a thin W layer at an antiferromagnet/ferromagnet (AFM/FM) interface, we enhance the annealing temperature to 355 °C and obtain a high tunnel magnetoresistance ratio of 127%. Subsequently, field-free spin–orbit torque (SOT) switching of perpendicular MTJ is realized thanks to the in-plane exchange bias generated at the AFM/FM interface. Moreover, by applying a gate voltage, a coercive field is effectively decreased due to the voltage-controlled magnetic anisotropy (VCMA) effect. Finally, through the interplay of the SOT and VCMA effects, the critical switching current density is dramatically reduced by 73% (to 2.4 MA/cm2) and the total writing power consumption is decreased by 84% when a gate voltage of 0.76 V is applied. These findings pave the way for the practical applications of the IrMn-based perpendicular MTJs in low-power magnetic random-access memory.

BIST-Supported Cryogenic Write Trimming With In-MRAM Computing Case Study

In the processor-memory separated von- Neumann computation paradigm, the “memory-wall” effect becomes critical due to large access latency and tremendous amount of data movement. In this work, we pursue cryogenic temperature based memory design and focus on spin-transfer-torque magnetoresistive random access memory (STT-MRAM) at 77-Kelvin (achieved with low-cost liquid nitrogen). Cryogenic compact model and its related cryogenic bit-cell are investigated, based on 77 K experiment data of magnetic tunnel junction (MTJ) and CMOS transistor. Compared with the simulated room temperature results, 70% reduction of sensing latency can be obtained at 0.7 V supply voltage, whereas writing latency and yield performance are significantly degraded. In order to overcome the above drawbacks, a novel joint trimming system is proposed including a build-in- self-test (BIST) block and a string of multi-stage level shifters (LS). A case study is executed with in-MRAM computing (IMC). Results show that cryogenic IMC with write trimming provides performance improvements of 33% on average, and concurrently reduces memory energy consumption by 70% on average. The proposed 77 K cryogenic design method can be further applied to other energy constrained applications.

Impact of Voltage Polarity on Time-Dependent Dielectric Breakdown of 1-nm MgO-Based STT-MRAM With Self-Heating Correction

Time-dependent dielectric breakdown (TDDB) lifetime of ultrathin (1 nm) MgO in spin-transfer torque magnetoresistive random access memory (STT-MRAM) devices has recently been shown to be driven by factors other than voltage alone. This study focuses on the specific role of asymmetry in the current flow for different polarity pulsing modes of voltage stress on the TDDB lifetime of 1-nm MgO. Numerical analysis, based on a 3-D heat-diffusion equation and spintronic simulations, has been performed to characterize the temperature rise in the devices for precise correction of self-heating to obtain a correct interpretation of MgO TDDB. It is shown that the different lifetimes for the positive and negative modes can be attributed to different temperature increases arising from self-heating. While the positive and negative modes displayed a non-Arrhenius behavior, the bipolar mode showed an Arrhenius trend in which we observed a unique bimodal behavior of TDDB activation energy ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${E}_{\text {a}}$ </tex-math></inline-formula> ) as a function of stress voltage in the ultrathin MgO stack. We discuss the role of additional driving forces, such as current, self-heating, charge trapping, and interface strain governing the breakdown mechanism along with the voltage effect.

The magnetization reversal driven by spin-orbit-assisted spin-transfer torque

As the data writing scheme of magnetization reversal driven by spin-transfer torque can overcome the shortcomings of traditional magnetic-field writing mechanism, it has become a mainstream way of implementing information writing in magnetic random access memory. However, the explosive growth of information shows higher requirements for data storage and information processing, thus magnetic random access memories based on spin-transfer torque data writing method pose several issues, including barrier reliability and limited storage speed. Recent experimental studies have shown that the spin-orbit torque through the spin Hall effect or Rashba effect in heavy-metal/ferromagnetic bilayer structures has the potential advantages in overcoming these limitations. They can also be used to drive magnetization to achieve rapid reversal. Especially, the three-terminal magnetic tunnel junction separates data reading from writing current. It has the advantages of faster writing speed and better stability and thus becomes the most promising magnetic storage technique at present. The magnetization reversal driven by spin-orbit-assisted spin-transfer torque in a three-terminal magnetic tunnel junction is studied theoretically in this work. By linearizing the Landau-Lifshitz-Gilbert equation with the additional spin-transfer torque term and spin-orbit torque term in the spherical coordinates, two coupled differential equations and the new equilibrium directions are obtained. With the stability analysis of the new equilibrium directions, the phase diagrams defined in parameter space spanned by the current densities of spin-transfer and spin-orbit torques are established. There are several magnetic states in the phase diagrams, including quasi-parallel stable states, quasi-antiparallel stable states, and bistable states. By adjusting the current density of the spin-transfer torque, the magnetization reversal between two stable states is realized. It is found that the magnetization reversal time is greatly reduced with the assisting of spin-orbit torque, and it decreases with the augment of current density of spin-orbit torque. Meanwhile, the zero-field magnetization reversal can be realized through the interplay between spin-orbit torque and spin-transfer torque. In addition, compared with the damping-like term of spin-orbit torque, the field-like one plays a leading role in magnetization reversal. The presence of field-like term of spin-orbit torque can also reduce the reversal time that decreases with the increase of the ratio of field-like torque to damping-like one.

Giant tunneling magnetoresistance in in-plane double-barrier magnetic tunnel junctions based on MXene Cr2C.

The discovery of two-dimensional (2D) magnetic materials makes it possible to realize in-plane magnetic tunnel junctions. In this study, the transport characteristics of an in-plane double barrier magnetic tunnel junction (IDB-MTJ) based on Cr2C have been studied by density functional theory combined with the nonequilibrium Green's function method. The results showed its maximum tunneling magnetoresistance ratio (TMR) value reached 6.58 × 1010. Its minimum TMR value (3.86 × 106) was also comparable to those of conventional field effect transistors (FETs). Due to its giant TMR and unique structural characteristics, the IDB-MTJ based on Cr2C has great potential applications in magnetic random access memory (MRAM) and logic computing.

A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System

Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel cell (MLC) STT-MRAM can further increase density by storing 2 bits in one cell’s hard and soft domain, respectively. However, MLC STT-MRAM suffers two-step write, leading to high write energy, long latency, and severe lifetime degradation. Current encoding techniques propose to encode the new data to reduce the two-step data writes. However, they have two weaknesses: 1) high area overhead, e.g., recent work TSE (Hsieh et al., 2020) needs extra 37.5% MLCs and 2) prolong the write latency due to an extra read. Therefore, we propose enhanced one-step write (EOSwrite) to write data in one step. EOSwrite includes line bypassing and four intraline encoding techniques. Line bypassing schemes can bypass the writes to zero or clean lines, leading to low write/read latency. As for the intraline techniques, we propose four write modes. They utilize the data patterns and the clean data in cache lines to write data in one step, therefore reducing the data write latency. The key idea of one-step write is to write as much data as possible in the soft domain of MLC STT-MRAM. EOSwrite can greatly relieve the weaknesses of the current encoding schemes. Evaluation results show that EOSwrite can improve the lifetime of MLC STT-MRAM by 56.96%, reduce dynamic energy by 33.95%, reduce access latency by 36.95%, and improve system performance of MLC STT-MRAM by 4.30%, respectively. While the area overhead of EOSwrite is only 7.27%.

Giant unilateral electric-field control of magnetic anisotropy in MgO/Rh2CoSb heterojunctions.

A large voltage-controlled magnetic anisotropy (VCMA) effect is highly desirable for applications of voltage-torque magnetic random access memory. In this work, the dependence of magnetic anisotropy (MA) on the electric field in a MgO-based heterojunction consisting of a new Heusler alloy, Rh2CoSb, is studied using first-principles calculations. We find that the Rh-terminated MgO/Rh2CoSb heterojunction has a perpendicular MA and a giant VCMA coefficient of 7024 fJ V-1 m-1. Furthermore, the VCMA coefficient shows a characteristic of dependence on the electric-field direction. The origins of these behaviors are elucidated by orbital-resolved MA and second-order perturbation theoretical analysis. As the spin-down states of the in-plane orbital, dxy, are close to the Fermi level, the shift of these states induced by the electric field gives rise to significant changes of magnetic anisotropy energy, which is mainly responsible for the giant VCMA effect.

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory

Sparse Code With Minimum Hamming Distance of Three for Spin-Torque Transfer Magnetic Random Access Memory