Time-domain computing for Boolean logic using STT-MRAM

Abstract

With the development of artificial intelligence, the separation of memory and processor in the traditional von-Neumann architecture has led to the bottleneck of data transmission hindering the development of energy efficient computing. The computing-in-memory (CIM) paradigm is expected to solve the problems of memory wall and power wall. In this work, we propose a time-domain (TD) computing scheme based on the spin transfer torque magnetic random access memory (STT-MRAM). Basic Boolean logic operations, such as AND/OR/Full-adder (FA), are implemented through converting the bit-line voltage to time delay and time-to-digital converter (TDC). The proposal is simulated using the 28 nm CMOS process and 40 nm MTJ compact model. Monte-Carlo simulations show that 94.2% to 100% computation accuracy can be obtained and the delay of AND/OR and FA is 2.5 ns and 3.5 ns. The energy consumption of AND/OR and FA achieve 59.43 fJ and 97.56 fJ, respectively.