Magnetic Tunnel Junction Devices Research Articles

Reduced Exchange Interactions in Magnetic Tunnel Junction Free Layers with Insertion Layers

Perpendicularly magnetized CoFeB layers with ultra-thin non-magnetic insertion layers are very widely used as the electrodes in magnetic tunnel junctions for spin transfer magnetic random access memory devices. Exchange interactions play a critical role in determining the thermal stability of magnetic states in such devices and their spin torque switching efficiency. Here the exchange constant of free layers incorporated in full magnetic tunnel junction layer stacks, specifically CoFeB free layers with W insertion layers is determined by magnetization measurements in a broad temperature range. A significant finding is that the exchange constant decreases significantly and abruptly with W insertion layer thickness. The perpendicular magnetic anisotropy shows the opposite trend; it initially increases with W insertion layer thickness and shows a broad maximum for approximately one monolayer (0.3 nm) of W. These results highlight the interdependencies of magnetic characteristics required to optimize the performance of magnetic tunnel junction devices.

Study on the effect of re-deposition induced by ion beam etching on MTJ performances

Magnetic tunnel junction (MTJ) as a key spintronics device can be used for the high-sensitivity magnetic field sensor and high-density non-volatile magnetic random access memory (MRAM). To obtain a high tunneling magnetoresistance (TMR), precise control of the etching process for MTJs is an essential step. In order to investigate the effect of the etching angle on the performance of MTJ devices, a series of MTJ pillars are fabricated by etching with the incidence angle of 10°, 20° and 30°. The prepared samples are characterized by the optical microscopy and SEM, and the R-H curves are also measured and then statistically analyzed. The results reveal that the performance of the MTJ is strongly affected by the IBE process, displaying the uniformity of the pillars edge and MTJ performance will improve as well with the increase of the etching angle. Then, a simplified model based on the re-deposition effect of the etching process is established to explain the experimental phenomena. Furthermore, a newly defined material parameter is introduced in this model and obtained with fitting the experimental results. This proves a valuable way to evaluate the quality of the MTJ stack film without the interference of the device fabrication process.

First-principles study on the structure, magnetism, and electronic properties in inverse Heusler alloy Ti2FeAl/GaAs(100) heterojunction

Abstract The interface structure stability, atomic displacement, atom-resolved magnetism, electronic properties, and spin polarization of 12 possible atomic terminations in Ti2FeAl/GaAs(100) heterojunction are comprehensively investigated by implementing the first-principles calculations. All of the lowest-energy interface structures are theoretically favorable to stability from interface formation energy examinations. The interface Fe atoms will shrink inwards, whereas the interface Ti atom will be moved outwards inversely. Therefore, an uneven interface atomic layer is observed in the heterojunction, which can lead to further spin-electronic scattering and reduction of the spin polarization. The competition among antiferromagnetic coupling between Fe and Ti atoms, d-electronic localization, and the relaxing effect of the interface metal atoms plays an important role in the atomic magnetic moment at the interface. The ideal half-metallicity observed in bulk has been destroyed by the undesirable interface states. In the TiAl-Ti-Ga-Top interface structure, the spin-polarization ratio reaches 77.2%, which suggests that the tunnel magnetoresistance value can be close to 300% at low temperature. The TiAl-Ti-Ga-Top interface structure with Ti-Ga atoms top-connected termination is a promising candidate for applications in magnetic tunnel junction devices.

Low power device design application by magnetic tunnel junctions in Magnetoresistive Random Access Memory (MRAM)

The spintronics techniques combines the spin degree and charge which gives rise to state of the art devices like magnetic tunnel junctions which are ultra-low power devices. It is proposed in the paper to evaluate magnetic tunnel junctions (MTJ) at the device level. The paper present an overview of fabrication process, while considering different aspects of the characteristics of MTJs, performance, challenges and a wide range of applications which are different from conventional CMOS technology. The MTJ devices are CMOS compatible for non-volatility, high stability and reliability. The MTJ device is a promising candidate for building non-volatile circuits for ultra- low power operation and fast switching speeds. The current approaches to design logic functionalities and memory devices with MTJs w include hybrid CMOS and MTJ circuits are also discussed in the paper. The results on the most robust magnetic tunnel junction with Resistance Area = 8 Ω-µm2 demonstrates that it satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp), breakdown-of voltage to edge more than 0.5 V, read-induced rate beneath 10−9, and with adequate write endurance, free of undesirable write endurance magnetic inversion. Also this paper demonstrates on the most vigorous MTJ with Resistance Area = 8 Ω-µm2 that satisfies the statistical requirements in parallel with high magnetic tunnel resistance greater than 15σ(Rp),breakdown-of voltage to edge more than 0.5 V, read-induced rate less than 10−9, and with adequate write endurance, and is free of undesirable write endurance magnetic inversion.

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop.

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by and the energy by . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks.

Spiking neural networks (SNNs) are of interest for applications for which conventional computing suffers from the nearly insurmountable memory-processor bottleneck. This paper presents a stochastic SNN architecture that is based on specialized logic-in-memory synaptic units to create a unique processing system that offers massively parallel processing power. Our proposed synaptic unit consists of strained magnetic tunnel junction (MTJ) devices and transistors. MTJs in our synapse are dual purpose, used as both random bit generators and as general-purpose memory. Our neurons are modeled as integrate-and-fire components with thresholding and refraction. Our circuit is implemented using CMOS 28-nm technology that is compatible with the MTJ technology. Our design shows that the required area for the proposed synapse is only [Formula: see text]. When idle, the synapse consumes 675 pW. When firing, the energy required to propagate a spike is 8.87 fJ. We then demonstrate an SNN that learns (without supervision) and classifies handwritten digits of the MNIST database. Simulation results show that our network presents high classification efficiency even in the presence of fabrication variability.

All Perpendicular Spin Nano-Oscillators with Composite Free Layer

Owing to improved thermal stability and scalability, materials with perpendicular magnetic anisotropy (PMA) are extremely attractive. The all perpendicular magnetic tunnel junction ([Formula: see text]-MTJ) devices are primarily devoted to spin transfer torque (STT)-induced switching and few works report their microwave emission. Here, we demonstrate the basic results of RF function in nanoscale [Formula: see text]-MTJ which has two different thickness free layers separated by atom-thick tungsten insertion. The ultrathin W spacer layer not only enables the two CoFeB free layers precess as a single layer but also greatly enhances the PMA which further induces high-emission frequency. The all perpendicular spin transfer torque nano-oscillator (STNO) exhibited high frequency (7.6[Formula: see text]GHz) and large current modulation capability of [Formula: see text] at moderate external magnetic field. Along with our previous work on STT switching utilizing the similar stack, such a multifunctional structure could bring low cost solutions to Internet of Things (IoT) network applications.

Novel metallization processes for sub-100 nm magnetic tunnel junction devices

In this work, a novel method consisting of side-wall passivation and a top-metal reveal process is proposed for spintronics devices based on magnetic tunnel junctions (MTJs). The method can efficiently protect ferromagnetic metals and magnesium oxide, which are the key materials of MTJs, and effectively establish electrical contact with the interconnect metals for perpendicular MTJs (p-MTJs). The scheme consists of the passivation of MTJs with dual dielectrics – silicon nitride and silicon oxide – followed by planarization and selective wet etching. The proposed integration scheme was successfully demonstrated with 80-nm-diameter p-MTJ devices.

High-Entropy STT-MTJ-Based TRNG

Hardware true random number generators (TRNGs) yield random numbers from physical processes. Traditionally, such devices are based on statistically random events such as thermal noise or other quantum phenomena. In this brief, we propose a novel TRNG design using a spin-transfer torque magnetic tunnel junction (MTJ) device. Our solution exploits the stochastic nature of the MTJ switching, and the behavior of an XOR gate dealing with probabilistic signals. We show that by using multiple MTJ devices, the proposed TRNG succeeds in filtering the negative effect of environmental changes as well as fabrication-induced variability and generates random sequences with high-entropy under any conditions.

Effects of Elastic Dephasing on Scaling of Ultra-Small Magnetic Tunnel Junctions

The study of the effects of scaling on magnetic tunnel junction (MTJ) devices has become an important topic in the field of spin-based memory devices. Here, we investigate the effect of elastic dephasing on trilayer and pentalayer MTJ considered at small transverse cross-sectional areas using the non-equilibrium Green's function spin transport formalism. We consider the structures with and without dephasing effects and clearly point out as to how the tunnel magnetoresistance effect gets affected by dephasing. We attribute the trends noted by analyzing the transmission spectra and hence the currents across the devices. Although dephasing affects the tunnel magnetoresistance ratio (TMR) values for both devices, we note that the obtained TMR values are still in a reasonable range that may not hinder their usability for practical applications.

Modeling of a Magnetic Tunnel Junction for a Multilevel STT-MRAM Cell

In the recent past, spin-transfer torque (STT) magnetic random access memories (MRAMs) have gained stupendous research interest with a potential to provide a solution for the on-chip memory applications. The prevailing single-level cell STT-MRAMs pose significant challenges due to scaling issues, making them unviable for the low-power and high-density embedded memory applications. This paper describes a pathway to design low-cost-per-bit, energy-efficient, and high-density multilevel cell (MLC) STT-MRAMs. This paper presents a model for magnetic tunnel junction (MTJ) devices based on in-plane magnetic anisotropy (IMA) and perpendicular magnetic anisotropy (PMA) using Verilog-A and elemental SPICE simulation framework. These MTJ devices are connected in series or parallel configuration to carry out a comparative performance analysis of series-MLC (sMLC) or parallel-MLC (pMLC) STT-MRAMs. The proposed model is validated using experimental results of IMA- and PMA-based sMLC and pMLC configurations, and the simulation results reveal a close agreement. The PMA-based pMLC configuration offers ultralow-voltage operation, least tunnel magnetoresistance degradations, and distinct presentation of resistance states, making it suitable for embedded memory applications.

Hardware Acceleration Implementation of Sparse Coding Algorithm With Spintronic Devices

Sparse coding provides a powerful means to perform feature extraction on high-dimensional data and recently has attracted broad interest for applications. However, it still suffers from a big challenge to realize real-time energy-efficient feature extraction with conventional CPUs/GPUs owing to its highly intensive computation. Benefitting from the non-volatility, low power, high speed, great scalability, and good compatibility with CMOS technology, spintronic devices, such as magnetic tunnel junction and domain wall motion (DWM) device, have been explored for applications, ranging from memory, logic, to neuromorphic computing. In this paper, we explore the possibility of hardware acceleration implementation of the sparse coding algorithm with spintronic devices by a series of design optimizations across the algorithm, architecture, circuit, and device. First, one sparse coding algorithm is selected well suited for parallelization and hardware acceleration. Then, a DWM-based compound spintronic device (CSD) is engineered and modeled, which is envisioned to achieve multiple conductance states. Sequentially, a parallel architecture is presented based on a dense cross-point array of the proposed DWM-based CSD, which can be envisioned to accelerate the selected sparse coding algorithm with a designed dedicated periphery read and write circuit owing to its massively parallel read and write operation. Experimental results show that the selected sparse coding algorithm can be accelerated by 1400× with the proposed parallel architecture in comparison with software implementation. Moreover, its energy dissipation is eight orders of magnitude smaller than that with software implementation. Additionally, an artificial neural circuit (ANC) with the proposed DWM-based CSD is also presented, which can achieve a multi-step transfer function. By using the proposed DWM-based CSD as a single synapse and the proposed ANC as one neuron, a fully forward-connected artificial neural network is constructed to classify the learned feature vectors, and the recognition error rate can reach 7.25%.

Area and Energy Efficient Series Multilevel Cell STT-MRAMs for Optimized Read–Write Operations

With the inception of perpendicular magnetic anisotropy-based magnetic tunnel junction (PMTJ) devices, spin-transfer torque (STT) magnetic random access memory (MRAM) is considered as a promising candidate for low power high-density embedded memory applications. However, the single-level cell STT-MRAM did not create much impact due to its energy/area inefficiency, higher cost per bit, and unoptimized read/write operations in sub-50 nm regime. In this paper, a series multilevel cell (sMLC) STT-MRAM is proposed that offers higher array density with reliable and energy efficient read–write operations with minimum error rates at the lower supply voltage. A high-k dielectric metal gate-based gate-all-around vertical silicon nanowire is used to drive the sMLC. A unified model based on Verilog-A and HSPICE is employed to imitate the PMTJ device. The results of 2 bit sMLC designs demonstrate switching error probability much below $10^{-9}$ , and average write energy <2 pJ at the pulsewidth of 20 ns with a footprint area of 2F2 per bit (F is the feature size).

Modeling and Evaluation of Sub-10-nm Shape Perpendicular Magnetic Anisotropy Magnetic Tunnel Junctions

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits.

Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices

A circuit optimization technique of nonvolatile logic-in-memory (NVLIM)-based lookup table (LUT) circuits in conjunction with magnetic-tunnel junction (MTJ) devices is proposed. Three important points should be considered for the circuit optimization technique of the NVLIM-based LUT circuit. One is optimizing DC and transient characteristics of the read current path, another is minimizing the effect of capacitance of both read-access transistors and write-access transistors, the other is how to design the selector circuit. As a typical example, the NVLIM-based LUT circuits is designed using 55 nm CMOS technology with two types of MTJ devices; the output delay, power and area of the circuit are evaluated. As a result, the output delay in the NVLIM-based 6-input LUT circuit is reduced by 47% compared to that of conventional SRAM-based implementation with 27% lower active power consumption as well as 67% of area reduction.

Design of MTJ-Based nonvolatile logic gates for quantized neural networks

Logic gates using magnetic tunnel junction (MTJ)-based nonvolatile logic-in-memory (NV-LIM) architecture are designed for quantized neural networks (QNNs) for Internet-of-Things applications. The NV-LIM-based implementation reduces data transfer costs between storage and logic gate components, thereby greatly enhancing the energy efficiency of inference operations in QNNs. The impact of the proposed nonvolatile logic gates for binary and ternary neural networks on energy consumption, delay, and area overhead reduction is demonstrated through circuit evaluations based on the parameters of the measured MTJ devices.

Magnetic domain wall neuron with lateral inhibition

The development of an efficient neuromorphic computing system requires the use of nanodevices that intrinsically emulate the biological behavior of neurons and synapses. While numerous artificial synapses have been shown to store weights in a manner analogous to biological synapses, the challenge of developing an artificial neuron is impeded by the necessity to include leaking, integrating, firing, and lateral inhibition features. In particular, previous proposals for artificial neurons have required the use of external circuits to perform lateral inhibition, thereby decreasing the efficiency of the resulting neuromorphic computing system. This work therefore proposes a leaky integrate-and-fire neuron that intrinsically provides lateral inhibition, without requiring any additional circuitry. The proposed neuron is based on the previously proposed domain-wall magnetic tunnel junction devices, which have been proposed as artificial synapses and experimentally demonstrated for non-volatile logic. Single-neuron micromagnetic simulations are provided that demonstrate the ability of this neuron to implement the required leaking, integrating, and firing. These simulations are then extended to pairs of adjacent neurons to demonstrate, for the first time, lateral inhibition between neighboring artificial neurons. Finally, this intrinsic lateral inhibition is applied to a ten-neuron crossbar structure and trained to identify handwritten digits and shown via direct large-scale micromagnetic simulation for 100 digits to correctly identify the proper signal for 94% of the digits.

Impact of operating temperature on the electrical and magnetic properties of the bottom-pinned perpendicular magnetic tunnel junctions

Analogous device parameters in both the parallel (P) and anti-parallel (AP) states ensure a symmetric spin-transfer-torque magnetic random-access memory operation scheme. In this study, however, we observe an increasing asymmetry in the performance metrics with operating temperature of the bottom-pinned perpendicular magnetic tunnel junction (p-MTJ) devices. A temperature-dependent increase in the contribution of the stray field is observed in the tunneling magnetoresistance loop analysis. The switching current for P-to-AP decreases by 30% in the thermally activated switching regime by increasing the temperature from 300 K to 400 K, while it remains similar for AP-to-P. In addition, with the same temperature range, the thermal stability factor for the P state decreases 20% more than that for the AP state. We attribute those observations to the increase in the overcompensation of the stray field from the synthetic anti-ferromagnet structure. Saturation magnetization (MS) of the [Co/Pt]x-based multilayers is much less affected by temperature [MS(400 K)/MS(300 K) = 97%] compared to that of the CoFeB-based multilayers (88%). Such an impact can be more severe during the electrical switching process due to the Joule heating effect. These results suggest that, to understand and to evaluate the performance in a wide range of temperatures, it is crucial to consider the contribution of the entire magnetic components in the p-MTJ stack.

Modular Compact Modeling of MTJ Devices

This paper describes a robust, modular, and physics- based circuit framework to model conventional and emerging Magnetic Tunnel Junction (MTJ) devices. Magnetization dynamics are described by the stochastic Landau-Lifshitz-Gilbert (sLLG) equation whose results are rigorously benchmarked with a Fokker-Planck Equation (FPE) description of magnet dynamics. We then show how sLLG is coupled to transport equations of MTJ-based devices in a unified circuit platform. Step by step, we illustrate how the physics-based MTJ model can be extended to include different spintronics phenomena, including spin-transfer-torque (STT), voltage-control of magnetic anisotropy (VCMA) and spin-orbit torque (SOT) phenomena by experimentally benchmarked examples. To demonstrate how our approach can be used in the exploration of novel MTJ-based devices, we also present a recently proposed MEMS resonator- driven spin-torque nano oscillator (STNO) that can reduce the phase noise of STNOs. We briefly elaborate on the use of our framework beyond conventional devices.

Energy-Efficient Design of Hybrid MTJ/CMOS and MTJ/Nanoelectronics Circuits

As CMOS technology scales down to the nanoscale, high leakage power consumption becomes one of the major concerns in the design of electronic circuits. To overcome this challenge, nano-emerging technologies and logic-in-memory (LIM) structures are being studied. Magnetic tunnel junction (MTJ) is an emerging spin-based device, which consumes very minimal leakage power in conjunction with CMOS transistors. In this paper, we propose a novel MTJ/CMOS design, which consumes low power and has lower delay than the existing LIM-based MTJ/CMOS designs. The proposed MTJ/CMOS designs have lower power and lower delay by charge sharing the output nodes during the pre-charge phase. The designs are simulated using 45 nm CMOS technology with perpendicular anistropy CoFeB/MgO MTJ model using a Cadence Spectre simulator. From the simulation results, we can see that the proposed MTJ/CMOS OR, AND, XOR, MUX, and full adder designs have 31.35%, 40.15%, 49.17%, 35.86%, and 42.62% lower power-delay-product, respectively, compared with the existing MTJ/CMOS designs. Furthermore, in this paper, we have also studied the usage of integrating nano-electronic devices, such as a carbon nanotube field-effect transistor and a Fin field-effect transistor, in the proposed circuits along with the MTJ devices.