Magnetic Tunnel Junction Devices Research Articles

Applications of Magnetoelectric Materials for Solid-State Devices

A pplications of M agnetoelectric M aterials for S olid -S tate D evices B S J Karthik Gururangan In 1947, three men, William Shockley, Walter Brattain, and John Barden, revolutionized the world of electronics by developing the first operational transistor. The transistor made the creation of the computer and other digital electronics possible, ushering in a new era of technology and earning the three men the 1956 Nobel Prize in Physics. Armed with the transistor, scientists and engineers (notably, those from Intel Corporation) developed faster, smaller, and more efficient microprocessors and RAM storage devices throughout the 1980s and 1990s. The development of solid-state storage devices and hard drives is of utmost importance for our increasingly electronic world. Within the last decade, computers have reached unprecedented operation speeds, but we are approaching a plateau. Recently, scientists have found that we cannot overcome this hurdle simply by fitting more and more transistors onto a chip; we must actually change the fabric of the device by creating new materials in a fashion that takes advantage of their inherent quantum electronic properties. Currently, hard drives operate by using the principle of magnetoresistance. Magnetoresistance describes the phenomenon of a magnetic polarization affecting the resistance of a material. Figure 1. Diagram of parallel and anti-parallel magnetic tunnel junction (MTJ) configurations (Tsymbal, 1999) In Figure 1, we can see that the magnetic tunnel junction (MTJ) consists of a thin insulator sandwiched by two magnets. The insulator has a thickness on the order of a few nanometers; therefore, electrons from one magnet can tunnel across the dielectric to the other magnet. Tunneling essentially means that every particle has a non-zero probability of traversing a solid boundary. While the mechanics of tunneling are not well understood, we do know that it is due to the wave-particle duality of matter; thus, tunneling is a purely quantum phenomenon and can only happen to very small particles such as electrons or quarks. When electrons traverse the boundary, they create a current and we can measure a resistance across the MTJ device. The number of electrons that will tunnel across the insulator is dictated by the relative orientations of the two magnets. Suppose that there are only two magnetic orientations: “left” and “right.” If both magnets have the same orientation, we call that the parallel state. If they point in opposite directions, they are in the anti-parallel state. Tunneling is highly encouraged in the anti-parallel state and suppressed in the parallel configuration (Nishimura, 2002). Thus, we can conclude that for a given potential, the anti- parallel state has a very low resistance while the parallel state has a high resistance. In hard disk drives, a read head applies a set voltage over many of these MTJ bits, measuring the resulting resistance of each one. It interprets a high resistance as a “1” state and a low resistance as a “0” state; thus, magnetoresistance directly leads to a digital interpretation. In the case of RAM (random-access memory), these bits are constantly being changed and re- interpreted over and over. The problem is that imparting these magnetic polarizations (a process called writing) utilizes an external magnetic field and is energetically inefficient given how many times the polarization changes. Recently, there has been a huge interest in a new class of materials called multiferroics. These materials exhibit two or more so-called “ferroic parameters”: ferroelectricity, ferromagnetism, and ferroelasticity. Current research suggests that using specific multiferroic materials in place of the magnets in Figure 1 can revolutionize computer memory systems and usher in a new era of quantum electronic technology. Before we can understand what the different ferroic parameters are and how they occur, we need to understand crystalline materials and crystal structure. When one thinks of crystals, one often pictures 1 • B erkeley S cientific J ournal • S ynthetics • S pring 2014 • V olume 18 • I ssue 2

Influence of Film Thickness on Magnetic Tunneling Junction Sensor with In-Plane/Out-of-Plane Sensing Capabilities

A magnetic tunnel junction (MTJ) sensor with out-of-plane or in-plane magnetized free layer to achieve a linear and hysteresis-free response is demonstrated. We show that two MTJ devices, with different magnetization arrangements in the free and reference layers, have different sensor responses. The sensor with out-of-plane magnetized free layer has in-plane sensing capability and that with the in-plane one has out-of-plane sensing capability. The present theoretical study based on the coherent rotation of the magnet moment in the free layer exhibits linear and nonlinear dependence of the sensitivity and sensing range, respectively, on the thickness of the free layer. These findings indicate that a sensor with high sensitivity can be achieved by precisely controlling the film thickness of the free layer.

Complementary 5T-4MTJ nonvolatile TCAM cell circuit with phase-selective parallel writing scheme

Towards a compact and process-variation-tolerant nonvolatile ternary content-addressable memory (TCAM), we propose a novel complementary cell structure with just five transistors and four magnetic tunnel junction (MTJ) devices (5T-4MTJ). The complementary cell structure enlarges output voltage swing of each cell circuit together with match-line voltage swing in word circuit constructed by many bits of cell circuits, which eliminates search errors. We also propose a novel bit-parallel writing scheme, called phase-selective parallel writing, for the cell circuit. Every data is written into a complementary MTJ-device pair in two phases by selectively asserting bit-lines during 0-write phase or 1-write phase, not directly assigning write data to the bit-lines. Consequently, the phase-selective parallel writing scheme enables four-phase write for the proposed 5T-4MTJ-based word circuit.

Reliability Analysis and Comparison of Implication and Reprogrammable Logic Gates in Magnetic Tunnel Junction Logic Circuits

Non-volatile logic is a promising solution to overcome the leakage power issue which has become an important obstacle to scaling of CMOS technology. Magnetic tunnel junction (MTJ)-based logic has a great potential, because of the non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed of the MTJ devices. Recently, by direct communication between spin-transfer-torque-operated MTJs, several realizations of intrinsic logic-in-memory circuits have been demonstrated for which the MTJ devices are used simultaneously as memory and computing elements. Here, we present a reliability analysis of the MTJ-based logic operations and show that the reliability is an essential prerequisite of these MTJ-based logic circuits. It is demonstrated that for given MTJ device characteristics, the implication logic architecture, a new kind of logic based on material implication, significantly improves the reliability of the MTJ-based logic as compared to the reprogrammable logic architecture which is based on the conventional Boolean logic operations AND, OR, etc. Implementing the implication gates in spin-transfer torque magnetic random access memory arrays provides pure electrical read/write and logic operations and also allows fan-out to multiple outputs.

ChemInform Abstract: Voltage‐Controlled Magnetic Anisotropy in Spintronic Devices

AbstractReview: 2 refs.

Reliability-Based Optimization of Spin-Transfer Torque Magnetic Tunnel Junction Implication Logic Gates

Recently, magnetic tunnel junction (MTJ)-based implication logic gates have been proposed to realize a fundamental Boolean logic operation called material implication (IMP). For given MTJ characteristics, the IMP gate circuit parameters must be optimized to obtain the minimum IMP error probability. In this work we present the optimization method and investigate the effect of MTJ device parameters on the reliability of IMP logic gates. It is shown that the most important MTJ device parameters are the tunnel magnetoresistance (TMR) ratio and the thermal stability factor Δ. The IMP error probability decreases exponentially with increasing TMR and Δ.

A 71%-Area-Reduced Six-Input Nonvolatile Lookup-Table Circuit Using a Three-Terminal Magnetic-Tunnel-Junction-Based Single-Ended Structure

A single-ended circuit using three-terminal magnetic tunnel junction (3T-MTJ) devices is proposed for a compact nonvolatile lookup-table (NV-LUT) circuit. The use of 3T-MTJ devices makes a high tunnel magneto-resistance ratio used in the circuit, because read-current path is separated from the write-current path. By utilizing single-ended circuit structure, the NV-LUT circuit becomes quite simple without reference circuit. In fact, the effective area of the proposed 6-input NV-LUT circuit is only 29% the size of the corresponding CMOS-based implementation using two-terminal-MTJ-based nonvolatile static random access memory cells, with a simulation program with integrated circuit emphasis (SPICE) simulation under a 90 nm CMOS technology.

Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory

AbstractAs the feature size of CMOS components scales down, the standby power losses due to high leakage currents have become a top concern for modern circuit design. Introducing non-volatility in logic circuits allows to overcome the standby power issue. Magnetic tunnel junctions (MTJs) offer a great potential, because of their non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed. This work proposes current- and voltage-controlled MTJ-based implication (IMP) logic gtes for future non-volatile logic-in-memory architecture. The MTJ-based implication logic realizes an intrinsic logic-in-memory known as “stateful” logic for which the MTJ devices serve simultaneously as memory elements and logic gates. Spintronic implication logic gates are analyzed by using a SPICE model for spin-transfer torque (STT) MTJs in order to show the reliability of the IMP operation. It has been demonstrated that the proposed current-controlled implication gate offers a higher performance (power and reliability) than the conventional voltage-controlled one. The realization of the spintronic stateful logic operations extends non-volatile electronics from memory to logical computing applications and opens the door for more complex logic functions to be realized with MTJ-based devices. We present a stateful logic circuit based on the common STT-MRAM architecture capable of performing material implication. As an application example, an IMP-based implementation of a full-adder is presented.

Impact of current paths on measurement of tunneling magnetoresistance and spin torque critical current densities in GaMnAs-based magnetic tunnel junctions

GaMnAs-based magnetic tunnel junction (MTJ) devices are characterized by in-plane and perpendicular-to-plane magnetotransport at low temperatures. Perpendicular-to-plane transport reveals the typical tunneling magnetoresistance (TMR) signal. Interestingly, a similar TMR signature is observed in the in-plane transport signal. Here, low-ohmic shunting of the MTJ by the top contact results in significant perpendicular-to-plane current paths. This effect allows the determination of TMR ratios of MTJs based on a simplified in-plane measurement. However, the same effect can lead to an inaccurate determination of resistance area products and spin torque critical current densities from perpendicular-to-plane magnetotransport experiments on MTJ pillar structures.

Magnetic Oscillations Driven by the Spin Hall Effect in 3-Terminal Magnetic Tunnel Junction Devices

We show that a direct current in a tantalum microstrip can induce steady-state magnetic oscillations in an adjacent nanomagnet through spin torque from the spin Hall effect (SHE). The oscillations are detected electrically via a magnetic tunnel junction (MTJ) contacting the nanomagnet. The oscillation frequency can be controlled using the MTJ bias to tune the magnetic anisotropy. In this 3-terminal device, the SHE torque and the MTJ bias therefore provide independent controls of the oscillation amplitude and frequency, enabling new approaches for developing tunable spin torque nano-oscillators.

VOLTAGE-CONTROLLED MAGNETIC ANISOTROPY IN SPINTRONIC DEVICES

Electric-field-control of magnetism can dramatically improve the energy efficiency of spintronic devices and enhance the performance of magnetic memories. More generally, it expands the range of applications of nonvolatile spintronic devices, by making them energetically competitive compared to conventional semiconductor solutions for logic and computation, thereby potentially enabling a new generation of ultralow-power nonvolatile spintronic systems. This paper reviews recent experiments on the voltage-controlled magnetic anisotropy (VCMA) effect in thin magnetic films, and their device implications. The interfacial perpendicular anisotropy in layered magnetic material stacks, as well as its modulation by voltage, are discussed. Ferromagnetic resonance experiments and VCMA-induced high-frequency magnetization dynamics are reviewed. Finally, we discuss recent progress on voltage-induced switching of magnetic tunnel junction devices and its potential applications to magnetic random access memory (MRAM).

Architectural Exploration to Enable Sufficient MTJ Device Write Margin for STT-RAM Based Cache

As a promising nonvolatile memory technology, magnetic tunnel junction (MTJ) based spin-torque transfer RAM (STT-RAM) has recently attracted much attention. However, recent device research suggested that, in order to maintain sufficient MTJ write margin to prevent device breakdown, MTJs may be subject to unconventionally high random write error rates (e.g., 10-3 and above) as memory cell size is being scaled down. In this paper, we aim to develop a STT-RAM cache design solutions that can effectively tolerate high MTJ write error rates at small performance and implementation cost, which makes it much easier to maintain sufficient MTJ write margin and hence push the STT-RAM scalability envelope. Using the full system simulator PTLsim and a variety of benchmarks, we show that the proposed architecture design can readily accommodate MTJ write error rate upto 2% at the penalty of less than 3% processor performance degradation, less than 10% silicon area overhead, and negligible energy consumption overhead.

Low frequency noise in La0.7Sr0.3MnO3 based magnetic tunnel junctions

Magnetic tunnel junctions based on manganites can exhibit a high tunneling magnetoresistance ratio due to the almost full spin polarization at the Fermi level. However, the performances of magnetic tunnel junction devices are also strongly linked to their noise characteristics. Here, we present a low frequency noise study on fully epitaxial La0.7Sr0.3MnO3/SrTiO3/La0.7Sr0.3MnO3/La0.66Sr0.33Mn0.995Ru0.005O3 tunnel spin valves with tunneling magnetoresistance ratios larger than 100%. We evidence non-conventional low frequency noise dependence on temperature related to the magnetic fluctuations and structural phase transitions in the structure. We present also a comparison with the low frequency noise exhibited in Fe/MgO/Fe magnetic tunnel junctions.

Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic Tunnel Junction and Metal–Oxide–Semiconductor Hybrid Structure

A nonvolatile logic element (NV-LE) using a magnetic tunnel junction (MTJ) and metal–oxide–semiconductor (MOS)-hybrid structure is proposed for a high-density field-programmable gate array with an instant-on capability. Since the output current level of a multiplexer tree including MTJ devices is directly evaluated and amplified by a single differential amplifier on the final stage of the LUT circuit, the number of wasted sense amplifiers is greatly reduced and a compact 4-input NV-LE can be implemented. Moreover, the use of dynamic current-mode logic based circuitry makes it possible a high-speed operation with low-active power dissipation due to the elimination of steady current-path. In fact, the proposed 4-input NV-LE reduces transistor counts to 63% with no performance degradation compared to those of a conventional complementary-MOS-based implementation.

Electric field effects in low resistance CoFeB-MgO magnetic tunnel junctions with perpendicular anisotropy

We have investigated the electric field effects in low resistance perpendicular magnetic tunnel junction (MTJ) devices and found that the electric field can effectively reduce the coercivity (Hc) of free layer (FL) by 30% for a bias voltage Vb = −0.2 V. In addition, the bias field (Hb) on free layer is almost linearly dependent on Vb yet independent on the device size. The demonstrated Vb dependences of Hc and Hb in low resistance MTJ devices present the potential to extend the scalability of the electric field assisted spin transfer torque magnetic random access memory and improve its access speed.

Magnetic tunnel junction design margin exploration for self-reference sensing scheme.

This work investigates the magnetic tunnel junction (MTJ) design requirements for the application of nondestructive self-reference sensing scheme, a novel sensing scheme featuring high tolerance of process variations, fast sensing speed, and no impact on device reliability. Unlike the conventional sensing scheme that requires a large TMR ratio and the uniform antiparallel and parallel resistances for MTJs, the nondestructive self-reference sensing scheme is more sensitive to the roll-off slope of MTJ's R-I or R-V curve. Our purpose is to provide a guidance to facilitate MTJ design used in the nondestructive self-reference scheme. In this work, we comprehensively investigate and analyze the design matrix by considering MTJ device physical properties, such as bias voltage dependent conductance, spin torque, etc. The manuscript suggests the approaches to optimize MTJ design for better trade-off between device properties and circuit design.

Six-input lookup table circuit with 62% fewer transistors using nonvolatile logic-in-memory architecture with series/parallel-connected magnetic tunnel junctions

A compact 6-input lookup table (LUT) circuit using nonvolatile logic-in-memory (LIM) architecture with series/parallel-connected magnetic tunnel junction (MTJ) devices is proposed for a standby-power-free field-programmable gate array. Series/parallel connections of MTJ devices make it possible not only to reduce the effect of resistance variation, but also to enhance the programmability of resistance values, which achieves a sufficient sensing margin even when process variation is serious in the recent nanometer-scaled VLSI. Moreover, the additional MTJ devices do not increase the effective chip area because the configuration circuit using MTJ devices is simplified and these devices are stacked over the CMOS plane. As a result, the transistor counts of the proposed circuit are reduced by 62% in comparison with those of a conventional nonvolatile LUT circuit where CMOS-only-based volatile static random access memory cell circuits are replaced by MTJ-based nonvolatile ones.

Magnetic Tunnel Junction-Based Spintronic Logic Units Operated by Spin Transfer Torque

Magnetic tunneling junction (MTJ)-based programmable logic devices have been proposed and studied for future reconfigurable and nonvolatile computation devices and systems. Spin transfer torque (STT)-based switching has advantages in device scaling compared to the field-switching mechanism. However, the previously proposed MTJ logic devices have operated independently and, therefore, are limited to only basic logic operations. Consequently, the MTJ device has only been used as an ancillary device, rather than the main computation device. As a result, the full benefits of MTJ-based computation have not been explored. New designs are needed to accelerate the development of the MTJ-based logic devices. Specifically the realization of direct communication between the MTJ devices is crucial to fully utilize the MTJ devices in the circuits to implement more advanced logic functions. In this paper, new MTJ-based spintronic logic units (building blocks) for spintronic circuits using the STT switching mechanism have been proposed and investigated, which includes the designs of a basic STT-MTJ logic cell, a direct communication between the MTJ logic cells, a three-MTJ logic unit and a spintronic logic circuit acting as an arithmetic logic unit.

Effect of Magnetic Tunneling Junction Sensor Size on Ferromagnetic Interlayer Coupling

In this paper, we present experimental results of the ferromagnetic interlayer coupling effect in magnetic tunnel junction devices. This investigation is focused on the sensor size dependency of the ferromagnetic interlayer coupling. The geometry-dependent magnetostatic edge-coupling contribution is estimated by micromagnetic simulation and then subtracted from the net coupling field in order to obtain the correlation between ferromagnetic interlayer coupling and the sensor size.

STT-RAM Cell Optimization Considering MTJ and CMOS Variations

Spin-transfer torque random access memory (STT-RAM) becomes a promising technology for future computing systems for its fast access time, high density, nonvolatility, and small write current. However, like all the other nanotechnologies, STT-RAM suffers from process variations and environment fluctuations, which significantly affect the performance and stability of magnetic tunneling junction (MTJ) devices. In this study, we combine magnetic and circuit simulations to quantitatively analyze the impacts of MTJ and CMOS variations on the STT-RAM designs. Both bit-to-bit and cycle-by-cycle variations are considered. A robust STT-RAM design flow is also proposed.