LUT Size Research Articles

Low complexity, high throughput, energy efficient, pipelined and reconfigurable ASIC realization architecture for multi-layer perceptron models

There has been continuously growing research interest in Artificial Neural Networks (ANNs) due to their vast acceptance in many real-world applications. This has led to the appearance of a variety of realization methods for multilayer perceptron (MLP) inference models. In this paper, we propose a generalized 3-stage, configurable, multiplier-less, massive parallel realization architecture for MLP inference models. We use offset binary coded distributive arithmetic (OBC-DA), which uses LUTs to reduce hardware requirements, to realize internal computing units of MLPs. The designing efforts to achieve a reduction in resource requirements are two-fold; (i) reduction in LUT size itself, which is achieved by exploiting symmetry induced by OBC-DA and thereby reducing LUT size by 50%, and (ii) reduction in total number of LUTs which is attained by sharing the LUTs. The resource efficiency of the proposed architecture is further improved by decomposing the LUTs into parallel and smaller LUTs. Moreover, the resource efficiency is also enhanced by utilizing the symmetry among the inputs in the MLP layer. The ASIC synthesis results for underlying MLPs establish that the proposed method for the realization of MLPs is much more efficient than the earlier reported methods and coincides with the findings of the generalized hardware-timing complexities.

Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

The efficient architectures of Two-Dimensional (2D) Finite Impulse Response (FIR) filters are proposed for image processing applications. The performance metrics such as power consumption, area, and delay of the architectures can be optimized using VLSI design. The 2D FIR filter architectures can be implemented using parallel or block processing to increase the filter throughput and to prune the number of clock cycles required for image processing. The symmetry in the filter coefficients decreases the number of multipliers, whereas the multiplier block is very complex and a power-consuming block in the filter architecture. In this work, two types of symmetric architectures such as diagonal symmetry and quadrantal symmetry filters are proposed. The remaining multipliers required for the filter architecture are replaced by Distributed Arithmetic (DA) logic. The memory-based DA reduces the LUT size and hence the area, power, and delay are reduced in the filter architecture. Block processing, symmetry, and DA concepts are introduced here to optimize the 2D FIR filter architecture. The proposed architectures are implemented in 45 nm CMOS technology using Cadence Genus Synthesis tools and area, delay, power, Area-Delay Product (ADP), and Power-Delay Product (PDP) results are obtained and compared with state-of-the-art works. The ADP value of the proposed diagonal symmetry architecture is decreased by a maximum of 73.34 %, and a minimum of 20.39 %, and the PDP value is decreased by a maximum of 90.28 %, and a minimum of 21.27 % when compared to the existing works. The ADP and PDP values of the proposed quadrantal symmetry are decreased by a minimum of 23.62 %, and 27.74 % when compared to existing works, respectively.

Floating-Point Inverse Square Root Algorithm Based on Taylor-Series Expansion

This brief describes a segmented structure to deal with inverse square root in floating-point digital calculation arithmetic, based on Taylor-Series expansion; it uses only the small number of their expansion terms to achieve a fast evaluation of these functions in high precision. Taylor-series expansions of the inverse square root are examined for several center points with their convergence ranges, and the inverse square root calculation algorithm trade-offs among accuracy, numbers of multiplications/additions/subtractions and LUT sizes are shown; the designer can choose the optimal algorithm for his digital inverse square root calculation, and build its conceptual dedicated hardware architecture design with the contents described here.

Low Latency and Efficient LUT Based Multiplier for DSP Applications

In digital signal processing memory based computation plays a vital role for DSP applications, which has multiplication with a fixed set of coefficient. LUT optimization for memory based multiplication can be done with these three computational techniques like Anti symmetry product coding (APC) and Odd multiple storage (OMS), combined APC-OMS. OMS technique with the modified APC-OMS based LUT multiplier can be discussed in terms of area and delay. These techniques are coded in VHDL language and synthesized in Xilinx ISE design suite 14.7. Thus, this proposes the APC-OMS based LUT multiplier can optimize the LUT size and consumes less area and obtains high speed when compared to other techniques. The proposed LUT based multiplier requires less significant area and less multiplication time than the canonical-signed-digit based multiplier.

Multi-LUTs method for canopy nitrogen density estimation in winter wheat by field and UAV hyperspectral

Unmanned aerial vehicle (UAV) based hyperspectral images linked to a radiative transfer model can provide a promising approach for high throughput monitoring of plant nitrogen (N) status. In this study, multiple lookup tables (Multi-LUTs), each LUT corresponding to one growth stage, were constructed based on the N-PROSAIL model, a radiative transfer model, and LUT size was optimized for improving computing efficiency. The objective is to use the constructed Multi-LUTs for estimating canopy N density (CND) in winter wheat. Results suggest that Multi-LUTs of leaf area index, leaf N density and two spectral indices (MSR and MCARI/MTVI2) in winter wheat demonstrate good performance of CND estimation; and LUTs with the optimal size of 6000 rows can yield good accuracy. The R2 and nRMSE values of the regression relationship between estimated and measured CND were 0.83 and 0.23 from field hyperspectral data, and 0.69 and 0.27 from UAV based hyperspectral imagery during the 2014–2015 growing season. CND by Multi-LUTs method was also accurately estimated from field hyperspectral data during the 2013–2014 growing season, with R2 and nRMSE values of 0.74 and 0.26. The estimation accuracy of CND based UAV data was a slightly lower than based field data. The resultant thematic CND map accurately exhibits CND variability at varying spatial and temporal scales. Results from this study confirmed the potential of combining UAV based hyperspectral imagery and physical optics approach for estimating CND in winter wheat.

SU‐F‐I‐60: ICC MIWG Displays: Final Recommendations for Visualization of Medical Content On Color Display Systems

Purpose:Use of color images in medical imaging has increased significantly the last few years. There is no agreement yet on what is an appropriate visualization framework for color medical images. This lack of standardization results into large variability of color appearance and makes consistency and quality assurance a challenge. The ICC Medical‐Imaging‐Working‐Group (MIWG) has defined recommendations for visualization of medical content on color display systems, whereby DICOM GSDF images, pseudo color images and color accurate images can all be presented effectively on the same display.Methods:The MIWG characterized a wide range of color display systems (consumer, professional and medical), and collected representative greyscale and color medical images. Simulations and bench testing was done to quantitatively compare the performance of various architectures and imaging pipelines in an ICC framework context. This allowed making recommendations on imaging pipeline architectures, and defining minimum requirements to guarantee minimum performance levels.Results:The ICC framework specification supports many possible architectures, profile types and pipeline characteristics. Numerous experiments have been performed to understand the effects related to choice of System design choices such as architecture, profile type (matrix, LUT, device, …) and pipeline specifications (eg. bit depth, LUT size). The impact of inaccurate estimation of display luminance/contrast/tone rendering curve has also been studied. Specific recommendations have been made related to system configuration, ICC framework/CMM, and calibration process.Conclusion:There is a need to standardize how medical color images need to be visualized. The ICC Medical Imaging Working Group has defined recommendations for visualization of medical content on color display systems. It has been shown that it is possible to achieve accurate greyscale, pseudo color and absolute color visualization of medical images by means of the ICC framework, at least when appropriate choices are made related to profile specification, imaging pipeline and calibration procedure.Tom Kimpe, employee Barco NV

Efficient Hardware Implementation of Real-time Rectification using Adaptively Compressed LUT

Rectification is used as a preprocessing to reduce the computation complexity of disparity estimation. However, rectification also requires a complex computation. To minimize the computing complexity, rectification using a lookup-table (R- LUT) has been introduced. However, since, the R- LUT consumes large amount of memory, rectification with compressed LUT (R-CLUT) has been introduced. However, the more we reduce the memory consumption, the more we need decoding overhead. Therefore, we need to attain an acceptable trade-off between the size of LUT and decoding overhead. In this paper, we present such a trade-off by adaptively combining simple coding methods, such as differential coding, modified run-length coding (MRLE), and Huffman coding. Differential coding is applied to transform coordinate data into a differential form in order to further improve the coding efficiency along with Huffman coding for better stability and MRLE for better performance. Our experimental results verified that our coding scheme yields high performance with maintaining robustness. Our method showed about ranging from 1 % to 16 % lower average inverse of compression ratio than the existing methods. Moreover, we maintained low latency with tolerable hardware overhead for real- time implementation.

Transformed HCT for parallel Huffman decoding

SummaryThis paper proposes a novel and generic Huffman code table (HCT) transform and a simple parallel Huffman decoding method. Codes of the original HCT are left‐aligned, reordered in value, and partitioned into sub‐bands. Two kinds of modification to the codes are introduced in order to reduce the number of sub‐bands. The Huffman decoder can be implemented with a minimized size of single LUT, and the parallel decoding can be completed easily, at a constant rate of up to one code per cycle. An example of MP3 decoder and AAC decoder has been designed to demonstrate the efficiency of the proposed method. Copyright © 2014 John Wiley & Sons, Ltd.

A New Method to Reduce the Size of Lut in Digital Frequency Synthesizer

In this paper, the principal and application of digital frequency synthesizer are analyzed firstly. Then, the phase truncation error of phase accumulator is discussed theoretically and is eliminated by the real-time scrambling code from Linear Feedback Shift Registers (LFSR) for the purpose of engineering. At last, a new method combined difference method with coarse and fine lookup table (LUT) is proposed to reduce the length and amplitude of LUT. From the simulation of the new method, it is found that the LUT is reduced from 2^14*16 bit to2^10*14 bit and 2^14*7 bit. Also, the spurious free dynamic range of the power of output signal is more than 100dBc.The method can meet the request of project efficiently and save a lot of cost.

Statistical Timing and Power Optimization of Architecture and Device for FPGAs

Process variation in nanometer technology is becoming an important issue for cutting-edge FPGAs with a multimillion gate capacity. Considering both die-to-die and within-die variations in effective channel length, threshold voltage, and gate oxide thickness, we first develop closed-form models of chip-level FPGA leakage and timing variations. Experiments show that the mean and standard deviation computed by our models are within 3% from those computed by Monte Carlo simulation. We also observe that the leakage and timing variations can be up to 3X and 1.9X, respectively. We then derive analytical yield models considering both leakage and timing variations, and use such models to evaluate the performance of FPGA device and architecture considering process variations. Compared to the baseline, which uses the VPR architecture and device setup based on the ITRS roadmap, device and architecture tuning improves leakage yield by 10.4%, timing yield by 5.7%, and leakage and timing combined yield by 9.4%. We also observe that LUT size of 4 gives the highest leakage yield, LUT size of 7 gives the highest timing yield, but LUT size of 5 achieves the maximum leakage and timing combined yield. To the best of our knowledge, this is the first in-depth study on FPGA architecture and device coevaluation considering process variation.

Modified VLSI implementation of DA-DWT for image compression

The wavelet transformation is a widely used technique for image processing application. Hence compared to traditional transforms such as the Fast Fourier Transform (FFT) and Discrete Cosine Transform (DCT), wavelet transform holds both time and frequency information, based on a multi-resolution analysis framework. There is a growing need to embed it into a real system. Field Programmable Gate Array (FPGA) implementation of Discrete Wavelet Transform (DWT) results in higher processing speed and lower costs when compared to other implementation methods. In this work a modified DA which performs low-pass and high-pass filtering improves the computational speed of DWT. A 9/7 filter is designed using modified DA architecture to perform low-pass and high-pass filtering. By using optimised DA architecture the LUT size is reduced from 29 to 24 locations in 9th order filter and 27 to 24 in 7th order filter. The design is verified in a Verilog HDL simulator and implemented on XILINX Virtex5 FPGA board.

Exploring Area and Delay Tradeoffs in FPGAs With Architecture and Automated Transistor Design

Field-programmable gate arrays (FPGAs) are used in a variety of markets that have differing cost, performance and power consumption requirements. While it would be ideal to serve all these markets with a single FPGA family, the diversity in the needs of these markets means that generally more than one family is appropriate. Consequently, FPGA vendors have moved to provide a diverse set of families that sit at different points in the area-speed-power design space. This paper aims to understand the circuit and architectural design attributes of FPGAs that enable tradeoffs between area and speed, and to determine the magnitude of the possible tradeoffs. This will be useful for architects seeking to determine the number of device families in a suite of offerings, as well as the changes to make between families. We explore a broad range of architectures and circuit designs and developed a transistor sizing tool that automatically optimizes each design. In this paper, we describe this tool and demonstrate that it achieves results that are comparable to past work but with vastly less effort. We then use the designs produced by the tool to explore the range of tradeoffs possible. We find that through architecture and transistor sizing changes it is possible to usefully vary the area of an FPGA by a factor of 2.0 and the performance of an FPGA by a factor of 2.1. We also observe that the range of area and delay tradeoffs possible by varying only the transistor sizing of a single architecture is larger than the ranges observed in past architectural experiments. In addition to transistor size, we note that LUT size is one of the most useful parameters for trading off area and delay.

APPLICATION-ADAPTIVE RECONFIGURATION OF MEMORY ADDRESS SHUFFLER FOR FPGA-EMBEDDED INSTRUCTION-SET PROCESSOR

Programmability requirement in reconfigurable systems necessitates the integration of soft processors in FPGAs. The extensive memory bandwidth sets a major performance bottleneck in soft processors for media applications. While the parallel memory system is a viable solution to account for a large amount of memory transactions in media processors, memory access conflicts caused by multiple memory buses limit the overall performance. We propose and evaluate the configurable memory address shuffler integrated in memory access arbiter for the parallel memory system in a soft processor. The novel address shuffling algorithm profiles memory access pattern of the application, produces the access conflict graph, relocates decomposed memory sub-pages based on the access conflict graph, and finally generates a synthesizable code of the address shuffler. The address shuffler efficiently translates the requested memory addresses into the shuffled addresses such that the amount of simultaneous accesses to the identical physical memory block diminishes. The reconfigurability of the address shuffler enables the adaptive address shuffling depending on the memory access pattern of an application running on the soft processor. The configurable address shuffler removes 80% of access conflicts on average for benchmarks where the hardware overhead of the shuffler is 1592 LUTs which is 14% of LUT size of the processor core.

FPGA Interconnect Topologies Exploration

This paper presents an improved interconnect network for Tree‐based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree‐based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR‐style Mesh.

IF–THEN Adder Application in Online DALUT Implementation

This paper presents the application of a proposed if-then rule based adder in implementing distributed arithmetic online lookup table (DALUT). The online DALUT development and implementation is a continuation of our previous work where we proposed this idea and use it in designing finite impulse (FIR) filter. In our LUT architecture we have been able to overcome the major disadvantage of the basic DA architecture reported as the exponential growth of the LUT size with the number of input variables. The if-then adder was proposed in another work where it shows an efficient performance when compared with the well known ripple carry adder (RCA) and the carry lookahead adder (CLA). The online DALUT with the if-then adder was applied in designing 70-tap finite impulse response pulse shaping filter and some other different order FIR filters. The design was coded with Verilog hardware description language (verilog HDL) and synthesized using the Xilinx technology after being simulated with ModelSim 7.5g. The synthesis report shows that the design preference when using the if-then adder more efficient than in the case of the RCA and CLA adder. The maximum frequency reached with the design using the if-then adder was 85.095MHz, whereas, when using CLA and RCA adders it 77.936MHz and 77.042MHz respectively. Finally the design has been successfully downloaded to Virtex-II FPGA fg456 and tested with the TLA5201 logic analyzer.

Circuits and architectures for field programmable gate array with configurable supply voltage

Field programmable gate arrays (FPGAs) with supply voltage (Vdd) programmability have been proposed recently to reduce FPGA power, where the Vdd-level can be customized for FPGA circuit elements and unused circuit elements can be power-gated. In this paper, we first design novel Vdd-programmable and Vdd-gateable interconnect switches with minimal number of configuration SRAM cells. We then evaluate Vdd-programmable FPGA architectures using the new switches. The best architecture in our study uses Vdd-programmable logic blocks and Vdd-gateable interconnects. Compared to the baseline architecture similar to the leading commercial architecture, our best architecture reduces the minimal energy-delay product by 54.39% with 17% more area and 3% more configuration SRAM cells. Our evaluation results also show that LUT size 4 gives the lowest energy consumption, and LUT size 7 leads to the highest performance, both for all evaluated architectures.

Interpolation errors on gray gradations caused by the three-dimensional lookup table method

Three-dimensional table interpolation techniques are now widely used in color management systems. These techniques are practical because complicated color conversions such as gamma conversion, matrix masking, under color removal, or gamut mapping can be executed at once by use of a three-dimensional lookup table (3D LUT). However, in some cases, the resultant interpolated reproduction of gradation has visible artifacts that degrade neutral and color gradations. Several research works concerning interpolation accuracy have been published. However, those articles have focused on an average color difference derived from experiments based on very few types of color conversions with no theoretical explanation. This paper describes a theoretical evaluation of errors and reproduced gradation curves using three-dimensional interpolation for several nonlinear color conversions. Two types of errors; conventional error and ripple error that is difference between piece-wise linear approximation and interpolated curves are defined, and gray gradation is used for an input image. The errors with a tetrahedral interpolation technique are also examined. Several nonlinear color conversions are tested and significant ripples have been found in case of the matrix-gamma with negative coefficients and minimum (MIN) function. The error goes down with decreasing of the distance between the lattice points (D), however, the decreasing rate is quite different. From these analyses we can get useful information about optimal 3D LUT sizes and which conversions are suitable for three-dimensional interpolation.

Area-efficient pulse-shaping 1:4 interpolated FIRfilterbased on LUT partitioning

The design of an area-efficient pulse-shaping 1:4 interpolation FIR filter with a partitioned LUT structure is described. Since the LUT block of the FIR filter occupies a large area relative to that of other blocks, in the proposed FIR filter design the LUT size is reduced by partitioning, exploiting coefficient symmetry, and sharing the partitioned LUTs by multiplexing input data streams. Experiments show that in the proposed filter the area is reduced by >40% compared to the popular single-architecture dual-channel filter. The proposed FIR filter produces optimised results in the QPSK modulator.