Implementation of block-based diagonal and quadrantal symmetry type 2D-FIR filter architectures using DA technique

Abstract

The efficient architectures of Two-Dimensional (2D) Finite Impulse Response (FIR) filters are proposed for image processing applications. The performance metrics such as power consumption, area, and delay of the architectures can be optimized using VLSI design. The 2D FIR filter architectures can be implemented using parallel or block processing to increase the filter throughput and to prune the number of clock cycles required for image processing. The symmetry in the filter coefficients decreases the number of multipliers, whereas the multiplier block is very complex and a power-consuming block in the filter architecture. In this work, two types of symmetric architectures such as diagonal symmetry and quadrantal symmetry filters are proposed. The remaining multipliers required for the filter architecture are replaced by Distributed Arithmetic (DA) logic. The memory-based DA reduces the LUT size and hence the area, power, and delay are reduced in the filter architecture. Block processing, symmetry, and DA concepts are introduced here to optimize the 2D FIR filter architecture. The proposed architectures are implemented in 45 nm CMOS technology using Cadence Genus Synthesis tools and area, delay, power, Area-Delay Product (ADP), and Power-Delay Product (PDP) results are obtained and compared with state-of-the-art works. The ADP value of the proposed diagonal symmetry architecture is decreased by a maximum of 73.34 %, and a minimum of 20.39 %, and the PDP value is decreased by a maximum of 90.28 %, and a minimum of 21.27 % when compared to the existing works. The ADP and PDP values of the proposed quadrantal symmetry are decreased by a minimum of 23.62 %, and 27.74 % when compared to existing works, respectively.