Low complexity, high throughput, energy efficient, pipelined and reconfigurable ASIC realization architecture for multi-layer perceptron models

Abstract

There has been continuously growing research interest in Artificial Neural Networks (ANNs) due to their vast acceptance in many real-world applications. This has led to the appearance of a variety of realization methods for multilayer perceptron (MLP) inference models. In this paper, we propose a generalized 3-stage, configurable, multiplier-less, massive parallel realization architecture for MLP inference models. We use offset binary coded distributive arithmetic (OBC-DA), which uses LUTs to reduce hardware requirements, to realize internal computing units of MLPs. The designing efforts to achieve a reduction in resource requirements are two-fold; (i) reduction in LUT size itself, which is achieved by exploiting symmetry induced by OBC-DA and thereby reducing LUT size by 50%, and (ii) reduction in total number of LUTs which is attained by sharing the LUTs. The resource efficiency of the proposed architecture is further improved by decomposing the LUTs into parallel and smaller LUTs. Moreover, the resource efficiency is also enhanced by utilizing the symmetry among the inputs in the MLP layer. The ASIC synthesis results for underlying MLPs establish that the proposed method for the realization of MLPs is much more efficient than the earlier reported methods and coincides with the findings of the generalized hardware-timing complexities.