Abstract
This paper presents an improved interconnect network for Tree‐based FPGA architecture that unifies two unidirectional programmable networks. New tools are developed to place and route the largest benchmark circuits, where different optimization techniques are used to get an optimized architecture. The effect of variation in LUT and cluster size on the area, performance, and power of the Tree‐based architecture is analyzed. Experimental results show that an architecture with LUT size 4 and arity size 4 is the most efficient in terms of area and static power dissipation, whereas the architectures with higher LUT and cluster size are efficient in terms of performance. We also show that unifying a Mesh with this Tree topology leads to an architecture which has good layout scalability and better interconnect efficiency compared to VPR‐style Mesh.
Highlights
The work presented in this paper can be divided into two parts
We proposed a Tree-based architecture with high interconnect and low logic utilizations
MCNC benchmark implementation, we showed that this architecture has better area efficiency than the common VPRStyle clustered Mesh
Summary
The work presented in this paper can be divided into two parts. In the first part, we present an improved Tree-based FPGA architecture. In the second part of the paper, the architecture presented in the first part is used for the improvement of connection blocks and intracluster interconnect topologies in a cluster-based Mesh FPGA architecture. The motivation behind the second part of the paper is the optimization of connection blocks and intracluster interconnect topologies in a cluster-based Mesh FPGA architecture. This means that we need 256×1024 switches to route clusters internal signals only, which is very expensive In this part, our first contribution corresponds to a joint optimization of connection blocks and intracluster interconnect topologies. We present the effect of LUT and cluster size on Tree-based FPGA, we evaluate architecture routability, and we compare it with the common VPR-Style Mesh architecture. We present the cluster-based Mesh FPGA architecture and we conclude this paper
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