Low Interface Trap Density Research Articles

Efficiency improvement of PERC solar cell using an aluminum oxide passivation layer prepared via spatial atomic layer deposition and post-annealing

In this study, Al2O3 thin films are deposited on p-type silicon using spatial atomic layer deposition with trimethylaluminum and H2O. The films are annealed in atmosphere (ATM), forming gas (FG) and nitrogen (N2) at temperatures of 300–750 °C. Effects of annealing gas ambient and temperature on structural, electrical, and passivation properties of Al2O3/Si are systematically investigated. The experimental results show that the ATM annealing leads to an interfacial silicon oxide more than two times thicker than that of the samples annealed in FG and N2. The ratio of tetrahedral AlO4 to octahedral AlO6 can be correlated to the negative fixed oxide charge density (Qf) near the interface of Al2O3/Si. The 600 °C ATM-annealed sample has the highest Qf of 3.23 × 1012 cm−1 and thus gives the best field effect passivation. The sample annealed in FG at 450 °C has the lowest interface trap density (Dit) of 3.98 × 1011 eV−1 cm−2, indicating that the hydrogen is more effective than oxygen for chemical passivation. Overall, the FG-annealed sample has the highest lifetime of 933.8 μs, showing that chemical passivation is the primary consideration. The ATM annealing requires higher temperatures (~600 °C) to reach the optimal passivation, whereas the FG and N2 annealing temperature is limited to 450 °C to avoid dehydrogenation. Finally, for passivated emitter and rear contact cell fabrication, the cell with FG annealing has the best conversion efficiency of 21.43%, which is 0.17 and 0.54 percentage point higher than that of the cells with ATM and N2 annealing, respectively.

Electrical Characteristics and pH Response of a Parylene-H Sensing Membrane in a Si-Nanonet Ion-Sensitive Field-Effect Transistor.

We report the electrical characteristics and pH responses of a Si-nanonet ion-sensitive field-effect transistor with ultra-thin parylene-H as a gate sensing membrane. The fabricated device shows excellent DC characteristics: a low subthreshold swing of 85 mV/dec, a high current on/off ratio of ~107 and a low gate leakage current of ~10−10 A. The low interface trap density of 1.04 × 1012 cm−2 and high field-effect mobility of 510 cm2V−1s−1 were obtained. The pH responses of the devices were evaluated in various pH buffer solutions. A high pH sensitivity of 48.1 ± 0.5 mV/pH with a device-to-device variation of ~6.1% was achieved. From the low-frequency noise characterization, the signal-to-noise ratio was extracted as high as ~3400 A/A with the lowest noise equivalent pH value of ~0.002 pH. These excellent intrinsic electrical and pH sensing performances suggest that parylene-H can be promising as a sensing membrane in an ISFET-based biosensor platform.

Atomic-layer deposition of crystalline BeO on SiC

For the first time, an epitaxial beryllium oxide (BeO) film was grown on 4H silicon carbide (4H-SiC) by atomic layer deposition (ALD) at a low temperature of 250 °C. The BeO film had a large lattice mismatch with the substrate (>7–8%), but it was successfully grown to a single crystal by domain-matching epitaxy (DME). The bandgap energy, dielectric constant, and thermal conductivity properties of crystalline BeO are suitable for power transistors that require low leakage currents and fast heat dissipation in high electric fields. Physical characterization confirmed the single-crystalline BeO (0 0 2). Raman analysis showed that the E1 and A1 phonon modes of ALD BeO were intermixed with the E2 and A1 phonon modes of SiC, resulting in a significant increase in phonon intensity. After heat treatment at a high temperature, a small amount of SiO2 interfacial oxide was formed but the stoichiometry of BeO was maintained. From the capacitance-voltage (C-V) curves, we obtained a dielectric constant of 6.9 and calculated a low interface trap density of 6 × 1010 cm−2·eV−1 using the Terman method at Ec-Et = 0.6 eV. The high bandgap, thermal conductivity, and excellent crystallinity reduced the dangling bonds at the interface of BeO-on-SiC.

Channel Engineering of Normally-OFF AlGaN/GaN MOS-HEMTs by Atomic Layer Etching and High-$\kappa$ Dielectric

In this letter, normally-OFF AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors with a threshold voltage of 2.2 V have been achieved by an atomic layer etching technique. Combined with surface passivation by atomic layer deposition of composite HfSiO high- $\kappa $ gate dielectric, a well-controlled gate-recess process with minimized surface damage results in improved interface properties with a low interface trap density of $2.8\times 10^{11}$ eV−1cm−2 and suppressed gate leakage current with a high current on/off ratio over 1011. A maximum current density of 518 mA/mm with an ON-resistance of 10.1 $\Omega \cdot \textsf {mm}$ and a high breakdown voltage of 1456 V at an OFF-state current density of $1~\mu \text{A}$ /mm are also achieved. In the meantime, the dynamic ${\text {R}}_{\mathrm {on}}$ is only 1.2 times the static ${\text {R}}_{\mathrm {on}}$ after OFF-state drain voltage stress of 120 V and 2.6 times after 300-V stress.

Crystalline SrZrO3 deposition on Ge (001) by atomic layer deposition for high-k dielectric applications

Heteroepitaxial growth of crystalline SrZrO3 (SZO) on Ge (001) by atomic layer deposition is reported. Ge (001) surfaces are pretreated with 0.5-monolayers (ML) of Ba and an amorphous ∼3-nm SZO layer is grown from strontium bis(triisopropylcyclopentadienyl), tetrakis (dimethylamido) zirconium, and water at 225 °C. This ∼3-nm layer crystallizes at 590 °C and subsequent SZO growth at 225 °C leads to crystalline films that do not require further annealing. The film properties are investigated using X-ray photoelectron spectroscopy, x-ray diffraction, aberration-corrected electron microscopy, and capacitance-voltage measurements of metal-oxide semiconductor capacitor structures. Capacitance-voltage measurements of the SrZrO3/Ge heterojunctions reveal a dielectric constant of 30 for SrZrO3 and a leakage current density of 2.1 × 10−8 A/cm2 at 1 MV/cm with an equivalent oxide thickness of 0.8 nm. Oxygen plasma pretreatment of Ge (001), Zintl layer formation with 0.5 ML Ba, and atomic deuterium post-growth treatment were explored to lower interface trap density (Dit) and achieved a Dit of 8.56 × 1011 cm−2 eV−1.

Borosilicate Glass (BSG) as Gate Dielectric for 4H-SiC MOSFETs

In this work, we investigate the effect of borosilicate glass (BSG) as gate dielectric on dielectric/4H-SiC interface traps and channel mobility in 4H-SiC MOSFETs. The interface trap characterization by C−ψs analysis and I-V characterization show lower fast interface trap density (Dit) as well as significant improvement of channel field-effect mobility on devices with BSG than that on devices with standard NO anneal. In addition, the results indicate interface trap density decreases with increasing B concentration at the interface of BSG/4H-SiC, which in turn, results in higher channel mobility.

Enhanced Performance of Field-Effect Transistors Based on Black Phosphorus Channels Reduced by Galvanic Corrosion of Al Overlayers.

Two-dimensional (2D)-layered semiconducting materials with considerable band gaps are emerging as a new class of materials applicable to next-generation devices. Particularly, black phosphorus (BP) is considered to be very promising for next-generation 2D electrical and optical devices because of its high carrier mobility of 200-1000 cm2 V-1 s-1 and large on/off ratio of 104 to 105 in field-effect transistors (FETs). However, its environmental instability in air requires fabrication processes in a glovebox filled with nitrogen or argon gas followed by encapsulation, passivation, and chemical functionalization of BP. Here, we report a new method for reduction of BP-channel devices fabricated without the use of a glovebox by galvanic corrosion of an Al overlayer. The reduction of BP induced by an anodic oxidation of Al overlayer is demonstrated through surface characterization of BP using atomic force microscopy, Raman spectroscopy, and X-ray photoemission spectroscopy along with electrical measurement of a BP-channel FET. After the deposition of an Al overlayer, the FET device shows a significantly enhanced performance, including restoration of ambipolar transport, high carrier mobility of 220 cm2 V-1 s-1, low subthreshold swing of 0.73 V/decade, and low interface trap density of 7.8 × 1011 cm-2 eV-1. These improvements are attributed to both the reduction of the BP channel and the formation of an Al2O3 interfacial layer resulting in a high- k screening effect. Moreover, ambipolar behavior of our BP-channel FET device combined with charge-trap behavior can be utilized for implementing reconfigurable memory and neuromorphic computing applications. Our study offers a simple device fabrication process for BP-channel FETs with high performance using galvanic oxidation of Al overlayers.

Impact of active layer thickness of nitrogen-doped In–Sn–Zn–O films on materials and thin film transistor performances

Nitrogen-doped indium tin zinc oxide (ITZO:N) thin film transistors (TFTs) were deposited on SiO2 (200 nm)/p-Si〈1 0 0〉 substrates by RF magnetron sputtering at room temperature. The structural, chemical compositions, surface morphology, optical and electrical properties as a function of the active layer thickness were investigated. As the active layer thickness increases, Zn content decreases and In content increases gradually. Meanwhile, Sn content is almost unchanged. When the thickness of the active layer is more than 45 nm, the ITZO:N films become crystallized and present a crystal orientation along InN(0 0 2) plan. No matter what the thickness is, ITZO:N films always display a high transmittance above 80% in the visible region. Their optical band gaps fluctuate between 3.4 eV and 3.62 eV. Due to the dominance of low interface trap density and high carrier concentration, ITZO:N TFT shows enhanced electrical properties as the active layer thickness is 35 nm. Its field-effect mobility, on/off radio and sub-threshold swing are 17.53 cm2 V−1 · s−1, 106 and 0.36 V/dec, respectively. These results indicate that the suitable thickness of the active layer can enhance the quality of ITZO:N films and decrease the defects density of ITZO:N TFT. Thus, the properties of ITZO:N TFT can be optimized by adjusting the thickness of the active layer.

Atomic Nature of the Growth Mechanism of Atomic Layer Deposited High-κ Y2O3 on GaAs(001)-4 × 6 Based on in Situ Synchrotron Radiation Photoelectron Spectroscopy.

Y2O3 was in situ deposited on a freshly grown molecular beam epitaxy GaAs(001)-4 × 6 surface by atomic layer deposition (ALD). In situ synchrotron radiation photoemission was used to study the mechanism of the tris(ethylcyclopentadienyl)yttrium [Y(CpEt)3] and H2O process. The exponential attenuation of Ga 3d photoelectrons confirmed the laminar growth of ALD-Y2O3. In the embryo stage of the first ALD half-cycle with only Y(CpEt)3, the precursors reside on the faulted As atoms and undergo a charge transfer to the bonded As atoms. The subsequent ALD half-cycle of H2O molecules removes the bonded As atoms, and the oxygen atoms bond with the underneath Ga atoms. The product of a line of Ga–O–Y bonds stabilizes the Y2O3 films on the GaAs substrate. The resulting coordinatively unsaturated Y–O pairs of Y2O3 open the next ALD series. The absence of Ga2O3, As2O3, and As2O5 states may play an important role in the attainment of low interfacial trap densities (Dit) of <1012 cm–2 eV–1 in our established reports.

AlGaN/GaN MIS-HEMTs With High Quality ALD-Al2O3 Gate Dielectric Using Water and Remote Oxygen Plasma As Oxidants

We demonstrate the electrical performances of AlGaN/GaN metal–insulator–semiconductorhigh electron mobility transistors (MIS-HEMTs) with high quality Al2O3 gate dielectric deposited by plasma enhanced atomic layer deposition using both H2O and remote O2 plasma as oxygen sources. Excellent gate-dielectric/GaN interface and Al2O3 film quality were obtained, resulting in a very small threshold voltage hysteresis and a low interface trap density. The MIS-HEMT device exhibited high on/off current ratio of $\sim 10^{10}$ , steep subthreshold slope, small gate leakage current, low dynamic on-resistance degradation, and effectively current collapse suppression. These results indicate that incorporating remote O2 plasma in the ALD-Al2O3 deposition process is an effective and simple way to provide high quality gate dielectric for the GaN MIS-HEMTs production

Epitaxial ZnO gate dielectrics deposited by RF sputter for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors

Radio frequency (RF)-sputtered ZnO gate dielectrics for AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) were investigated with varying O2/Ar ratios. The ZnO deposited with a low oxygen content of 4.5% showed a high dielectric constant and low interface trap density due to the compensation of oxygen vacancies during the sputtering process. The good capacitance–voltage characteristics of ZnO-on-AlGaN/GaN capacitors resulted from the high crystallinity of oxide at the interface, as investigated by x-ray diffraction and high-resolution transmission electron microscopy. The MOS-HEMTs demonstrated comparable output electrical characteristics with conventional Ni/Au HEMTs but a lower gate leakage current. At a gate voltage of −20 V, the typical gate leakage current for a MOS-HEMT with a gate length of 6 μm and width of 100 μm was found to be as low as 8.2 × 10−7 mA mm−1, which was three orders lower than that of the Ni/Au Schottky gate HEMT. The reduction of the gate leakage current improved the on/off current ratio by three orders of magnitude. These results indicate that RF-sputtered ZnO with a low O2/Ar ratio is a good gate dielectric for high-performance AlGaN/GaN MOS-HEMTs.

Passivation of Ge/high-κ interface using RF Plasma nitridation

In this paper, plasma nitridation of a germanium surface using NH3 and N2 gases is performed with a standard RF-PECVD method at a substrate temperature of 250 °C. The structural and optical properties of the Ge surface have been investigated using Atomic Force Microscopy (AFM), Fourier Transform Infrared Spectroscopy (FT-IR), and Variable Angle Spectroscopic Ellipsometery (VASE). Study of the Ge (100) surface revealed that it is nitrated after plasma treatment while the GeO2 regrowth on the surface has been suppressed. Also, stability of the treated surface under air exposure is observed, where all the measurements were performed at room ambient. The electrical characteristics of fabricated Al/Ti/HfO2/GeON/p-Ge capacitors using the proposed surface treatment technique have been investigated. The C-V curves indicated a negligible hysteresis compared to ∼500 mV observed in untreated samples. Additionally, the C-V characteristic is used to extract the high-κ/Ge interface trap density using the most commonly used methods in determining the interface traps. The discussion includes the Dit calculation from the high-low frequency (Castagné–Vapaille) method and Terman (high-frequency) method. The high-low frequency method indicated a low interface trap density of ∼2.5 × 1011 eV−1.cm−2 compared to the Terman method. The J-V measurements revealed more than two orders of magnitude reduction of the gate leakage. This improved Ge interface quality is a promising low-temperature technique for fabricating high-performance Ge MOSFETs.

Side-by-Side Comparison of Single- and Dual-Active Layer Oxide TFTs: Experiment and TCAD Simulation

Single-active layer (SAL) and dual-active layer (DAL) oxide thin-film transistors (TFTs) are fabricated using the same process conditions and compared side by side. The SAL channel consists of amorphous In–Ga–Zn–O (a-IGZO), and the DAL of ultrathin In–Sn–O and a-IGZO. The DAL TFT exhibits strongly improved performance compared to the SAL TFT such as higher mobility of 31 cm $^{\textsf {2}}\cdot \text{V}^{-\textsf {1}}\cdot \text{s}^{-\textsf {1}}$ , smaller subthreshold swing of 175 mV/dec, and better positive bias temperature stress stability. Technology computer-aided design simulation is used to investigate the SAL and DAL device performance. A mapping technique is used to directly correlate the transfer characteristics to the subbandgap density of states. The simulation suggests that the improved performance of the DAL TFT is due to an improved gate insulator/channel interface with an approximately one order of magnitude lower interface trap density.

High-performance a-IGZO thin-film transistor with conductive indium-tin-oxide buried layer

In this study, we fabricated top-contact top-gate (TCTG) structure of amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistors (TFTs) with a thin buried conductive indium-tin oxide (ITO) layer. The electrical performance of a-IGZO TFTs was improved by inserting an ITO buried layer under the IGZO channel. Also, the effect of the buried layer’s length on the electrical characteristics of a-IGZO TFTs was investigated. The electrical performance of the transistors improved with increasing the buried layer’s length: a large on/off current ratio of 1.1×107, a high field-effect mobility of 35.6 cm2/Vs, a small subthreshold slope of 116.1 mV/dec, and a low interface trap density of 4.2×1011 cm−2eV−1 were obtained. The buried layer a-IGZO TFTs exhibited enhanced transistor performance and excellent stability against the gate bias stress.

Thermally oxidized 2D TaS2 as a high-κ gate dielectric for MoS2 field-effect transistors

We report a new approach to integrating high-κ dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered two-dimensional (2D) TaS2. Combined x-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance–voltage (C–V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2 V−1 s−1 at room temperature, indicating high dielectric quality and low interface trap density.

Enhancement of effective dielectric constant using high-temperature mixed and sub-nano-laminated atomic layer deposited Y2O3/Al2O3 on GaAs(001)

In-situ atomic layer deposition (ALD) Y2O3/Al2O3 in bi-layered and sub-nano-laminated structures were stacked on pristine GaAs(001) substrates for fabricating metal-oxide-semiconductor capacitors. The bi-layered Y2O3/Al2O3 showed an enhanced effective dielectric constant from 11.1 to 15.6 in capacitance-voltage characteristics with post deposition annealing to 900°C. No new oxide phase formed as carefully examined using synchrotron radiation X-ray diffraction and cross-sectional high-resolution scanning tunneling electron microscopy. We designed and grew sub-nano-laminated Y2O3/Al2O3 multi-layers to simulate the mixing of gate oxides, and observed an enhanced dielectric constant of 14.8 for the as-deposited sample. Both high-temperature mixed and sub-nano-laminated ALD Y2O3/Al2O3 exhibit high dielectric constant, low leakage current ~10−8A/cm2 and low interfacial trap density with GaAs(001), promising for high κ applications in future GaAs metal-oxide-semiconductor devices.

Analysis of border and interfacial traps in ALD-Y2O3 and -Al2O3 on GaAs via electrical responses - A comparative study

Y2O3 and Al2O3 were in-situ atomic layer deposited (ALD) on pristine GaAs(001)-4×6 reconstructed surfaces without surface pretreatments. We have studied the border and interfacial traps in both hetero-structures using the measured electrical responses. On the basis of frequency dispersion analysis of the capacitance-voltage (CV) characteristics, we conclude that Y2O3 has effectively passivated GaAs surface with a much lower interfacial trap density (Dit) than Al2O3 as the gate dielectric. The quasi-static CV and conductance measurements are in agreement with the above conclusion. We have demonstrated an excellent ALD-Y2O3/GaAs interface with low Dit's of (0.5–2)×1012eV−1cm−2 through the whole GaAs band gap without a mid-gap peak feature.

Ultra-high thermal stability and extremely low Dit on HfO2/p-GaAs(001) interface

Molecular beam epitaxy (MBE) HfO2 films ~1.5nm thick were directly deposited on freshly grown GaAs(001)-4×6 reconstructed surfaces. The hetero-structure exhibits outstanding thermal stability up to 900°C with excellent capacitance-voltage (C-V) and leakage current density-electric field (J-E) characteristics. We have extracted low interfacial trap densities (Dit's) with minimum value of 1.3×1011 eV−1cm−2 from the measured quasi-static C-V (QSCV) characteristics. The smallest frequency dispersion of the C-Vs for the MBE-HfO2/p-GaAs(001) is ~5.2% at frequency range of 500 to 1MHz and no trap-induced humps were observed in the C-Vs, as measured at 100°C and 150°C. Also, the leakage current density remains low of 10−8(A/cm2) at E<±3 (MV/cm). The key to passivate GaAs in attaining low Dit's and high-temperature thermal stability is to ensure the cleanness of GaAs surface prior to the high-κ deposition.

Capacitance-voltage characterization of Al2O3/GaN-on-insulator (GaNOI) structures with TMAH surface treatment

The capacitance-voltage (C-V) characterizations of Al2O3/GaN-on-insulator (GaNOI) structure, prepared with the Smart Cut™ technology, with and without tetramethylammonium hydroxide (TMAH) surface treatment have been investigated. The GaNOI structure consists of a 150nm-thick GaN layer and a 800μm-thick Si3N4/SiO2 buried insulating layer deposited on sapphire substrate. For fabrication of the MIS capacitor, an Al2O3 layer with thickness of 28nm as a gate dielectric was deposited on the GaNOI wafer by atomic layer deposition (ALD). The calculated carrier concentration of the GaN layer on the buried insulator was increased to 2.8×1017cm−3 from the value of ~5×1016cm−3 for the as-grown undoped GaN layer prior to the wafer transfer. The MIS capacitor with TMAH surface treatment showed a positive threshold voltage shift with negligible hysteresis and low interface trap density compared to the capacitor without TMAH surface treatment. Severe frequency dispersion was observed regardless of the TMAH treatment due to the crystal defects generated during the complicated wafer transfer process.

Demonstration of 2e12 cm− 2 eV− 1 2D-oxide interface trap density on back-gated MoS2 flake devices with 2.5 nm EOT

This study reports on the low interface trap density obtained from MOS capacitors and transistors with 2.5nm EOT using MoS2 flakes in back-gated configuration. Design ideology to measure thin flake structures is explained. CV measurements on MOSCAPs show Si-high-k like behavior with a midgap Dit of 2e12cm−2eV−1. By using CV measurements, the thickness of the MoS2 layer was also extracted.