Low Resource Usage Research Articles

Design and Implementation of Deduplication on F2FS

Data deduplication technology has gained popularity in modern file systems due to its ability to eliminate redundant writes and improve storage space efficiency. In recent years, the flash-friendly file system (F2FS) has been widely adopted in flash memory-based storage devices, including smartphones, fast-speed servers, and Internet of Things. In this article, we propose F2DFS (deduplication-based F2FS), which introduces three main design contributions. First, F2DFS integrates inline and offline hybrid deduplication. Inline deduplication eliminates redundant writes and enhances flash device endurance, while offline deduplication mitigates the negative I/O performance impact and saves more storage space. Second, F2DFS follows the file system coupling design principle, effectively leveraging the potentials and benefits of both deduplication and native F2FS. Also, with the aid of this principle, F2DFS achieves high-performance and space-efficient incremental deduplication. Third, F2DFS adopts virtual indexing to mitigate deduplication-induced many-to-one mapping updates during the segment cleaning. We conducted comprehensive experimental comparisons between F2DFS, native F2FS, and other state-of-the-art deduplication schemes, using both synthetic and real-world workloads. For inline deduplication, F2DFS outperforms SmartDedup, Dmdedup, and ZFS, in terms of both I/O bandwidth performance and deduplication rates. And for offline deduplication, compared to SmartDedup, XFS, and BtrFS, F2DFS shows higher execution efficiency, lower resource usage, and greater storage space savings. Moreover, F2DFS demonstrates more efficient segment cleanings than native F2FS.

Real-time fusion multi-tier DNN-based collaborative IDPS with complementary features for secure UAV-enabled 6G networks

UAV-enabled Integrated Sensing and Communication (ISAC) in sixth-generation (6G) wireless networks has sparked significant research interest. UAVs are positioned as aerial wireless platforms, extending coverage and improving Sensing and Communication (S&C) services. However, integrating UAVs introduces vulnerabilities due to multi-connectivity, necessitating robust security measures. To address this, efforts are focused on developing effective Intrusion Detection Systems (IDS). Here ML-based IDSs depend on the most suited Machine Learning (ML) algorithms for improved detection accuracy. However, inadequate detection features frequently contribute to the limitations of detection accuracy in various emerging cyber-attacks. Our study explores attack traits in UAV-enabled 6G networks, using complementary detection features to enhance ML-based attack detection. Additionally, existing Deep Neural Network (DNN) solutions for UAVs-enabled 6G networks mainly use single models (e.g., CNN, SVM, CGAN) instead of multi-tier models, (e.g., Hybrid, Fusion, Ensemble). Here, although the use of a single model can be faster for computer systems, it is difficult to understand the growing complexity of intrusion patterns in data. Also, these single models might not be good at recognizing the unique patterns of less common issues in datasets. Thus, we propose a fusion multi-tier DNN-based Collaborative Intrusion Detection and Prevention System (CIDPS) for critical UAV-enabled 6G networks. This system boosts accuracy without sacrificing latency reductions. Our approach learns decision boundaries from imbalanced data points using preceding DNNs sequentially. Moreover, most existing research works do not focus on intrusion prevention methods and deployment frameworks for UAV networks. This research proposes effective IPS mechanisms and deployment architecture for CIDPS in UAV-enabled 6G networks. It incorporates a CIDPS with an emergency response protocol, neutralizing attacks upon anomaly detection. We validate our solution through diverse dataset experiments (UAVIDS-2020, NF-UQ-NIDS-v2, 5G-NIDD). Unlike traditional practices where IDS are simulated, we implement CIDPS on actual UAV devices (PX4 Vision Dev Kit V1.5, DJI mini se, DJI mini 3 pro) and real-world UAV networks. Our approach outperforms prior algorithms with a 99.25% attack classification accuracy, higher detection efficiency, and lower resource usage, exceeding 99.05% detection rates.

Impacto de la telemonitorización como sistema para una adecuada titulación y adaptación de la CPAP domiciliaria en la apnea obstructiva del sueño (proyecto T-CPAP)

IntroductionContinuous Positive Airway Pressure (CPAP) constitutes the most effective treatment for Obstructive Sleep Apnea (OSA). Automatic titration systems (ATS) are predominantly used to achieve adaptation to the equipment. Home CPAP devices allow telemonitoring (TM) of the same parameters as those provided by ATS but with access to continuous usage data. Under this premise, we conducted a study on the potential validity of TM for home CPAP devices as a titration system, its direct impact on proper adaptation (AD) to the equipment, and secondarily on the healthcare resources employed to achieve it. Material and methodsAn observational study involving 318 patients with OSA who were titrated using TM to achieve AD to CPAP. Patients with OSA were consecutively recruited and evaluated at 1, 3, and 6 months after initiating treatment. Results were compared with a historical group of 307 patients with OSA who achieved AD to CPAP using ATS. Additionally, we assessed the impact on required healthcare resources. ResultsPatients with OSA who initiated CPAP treatment with TM over the first six months showed a similar AD rate compared to the historical group titrated using ATS, with lower resource usage in the TM group. ConclusionData provided by TM of home CPAP devices allow for titration and achieving similar AD as with ATS in non-complex patients.

Optimizing Medical IoT Disaster Management with Data Compression

In today's technological landscape, the convergence of the Internet of Things (IoT) with various industries showcases the march of progress. This coming together involves combining diverse data streams from different sources and transmitting processed data in real-time. This empowers stakeholders to make quick and informed decisions, especially in areas like smart cities, healthcare, and industrial automation, where efficiency gains are evident. However, with this convergence comes a challenge – the large amount of data generated by IoT devices. This data overload makes processing and transmitting information efficiently a significant hurdle, potentially undermining the benefits of this union. To tackle this issue, we introduce "Beyond Orion," a novel lossless compression method designed to optimize data compression in IoT systems. The algorithm employs advanced techniques such as Lempel Ziv-Welch and Huffman encoding, while also integrating strategies like pipelining, parallelism, and serialization for greater efficiency and lower resource usage. Through rigorous experimentation, we demonstrate the effectiveness of Beyond Orion. The results show impressive data reduction, with up to 99% across various datasets, and compression factors as high as 7694.13. Comparative tests highlight the algorithm's prowess, achieving savings of 72% and compression factor of 3.53. These findings have significant implications. They promise improved data handling, more effective decision-making, and optimized resource allocation across a range of IoT applications. By addressing the challenge of data volume, Beyond Orion emerges as a significant advancement in IoT data management, marking a substantial step towards realizing the full potential of IoT technology.

Efficient FPGA Binary Neural Network Architecture for Image Super-Resolution

Super-resolution systems refer to computer-based systems designed to enhance the quality of images or video by producing high-resolution renditions from low-resolution counterparts using computational algorithms and technologies. Various methods and techniques have been used in development of super-resolution systems. The development of Convolution Neural Networks (CNNs) and the Deep Learning (DL) methods have outperformed traditional methods. However, as models become increasingly deeper with wider receptive fields, the number of parameters significantly increases. While this often results in better performance, it renders these models impractical for real-life scenarios such as smartphones or other mobile systems. Currently, most proposed methods with higher perceptual quality demand a substantial amount of time to process a single image, even on powerful hardware like NVIDIA GPUs. Such computationally expensive models are not cost-effective for real-world application scenarios. Optimization is needed to reduce the computational costs and memory requirements to enhance their suitability for less powerful hardware configurations. In this work, we propose an efficient binary neural network architecture, ResBinESPCN, designed for image super-resolution. In our design, we improved the energy efficiency of the architecture through algorithmic and hardware-level optimizations. These optimizations not only enhance computational efficiency and reduce memory consumption but also achieve effective image super-resolution in resource-constrained environments. Our experimental validation highlights the effectiveness of this network structure and includes ablation studies on models with varying data bit widths. Hardware analysis substantiates the efficiency and real-time capabilities of this model. Additionally, deploying the model on FPGA using FINN demonstrates its low hardware resource usage and low power consumption.

FastNet: A feature aggregation spatiotemporal network for predictive learning

Spatiotemporal prediction is a challenging topic because of uncertainty. Existing works attempt to design complicated systems to learn short-term and long-term dynamics. However, these models suffer from heavy computational burden on spatiotemporal data, especially for high-resolution frames. To reduce resource dependence, we propose FastNet, a novel and light encoder–decoder for predictive learning. We stack four ConvLSTM (Convolutional Long Short-Term Memory) based layers to construct a hierarchical framework. Based on this architecture, the feature aggregation module first aligns the temporal context, then decouples different frequency information, next gathers multi-level features and last synthesizes new feature maps alternately. We aggregate various and hierarchical features into predictions bringing two benefits: rich multi-level features and low resource usage. As for the unit blocks, depth-wise separable convolution is used to improve model efficiency and compress model size. Besides, we adopt perceptual loss as the cost function between ground truths and predictions, which helps our model to get higher similarity with true frames. In experiments, we evaluate the performances of FastNet on the MovingMNIST (Mixed National Institute of Standards and Technology) and Radar Echo datasets to verify its effectiveness. The quantitative metrics on the Radar Echo dataset show that FastNet reaches a slight increase in accuracy but up to 84% decline in computation compared with PredRNN-V2. Therefore, our FastNet achieves competitive results with lower resource usage and fewer parameters than the state-of-the-art model.

A multi-channel TDC-in-FPGA with 150 ps bins for time-resolved readout of Cherenkov photons

This work presents a multi-channel TDC designed on a KINTEX-7 FPGA and which is used during the development phase of a new RICH photodetection system in view of a future LHCb upgrade. This TDC-in-FPGA core achieves a 150 ps bin width while keeping a low resource usage. It is capable of measuring time-over-threshold (ToT) and time-of-arrival (ToA) at a rate above 50 MHz. This core was embedded in a larger readout system and it was used during beam tests and in the laboratory to demonstrate the capabilities of a time-resolved readout system for compact RICH detectors.

A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability

In this work we propose a novel implementation on recent Xilinx FPGA platforms of a PUF architecture based on the NAND SR-latch (referred to as NAND-PUF in the following) which achieves an extremely low resource usage with very good overall performance. More specifically, a 4 bit NAND-PUF macro has been designed referring to the Artix-7 platform occupying only 2 slices. The optimum excitation sequence has been determined by analysing the reliability versus the excitation time of the PUF cells under supply voltage variations. A 128 bit NAND-PUF has been tested on 16 FPGA boards under supply voltage and temperature variations and measured performances have been compared against state-of-the-art PUFs from the literature. The comparison has shown that the proposed PUF implementation exhibits the best reliability performance while occupying the minimum FPGA resource usage achieved in the PUF literature.

A Reconfigurable Coprocessor for Simultaneous Localization and Mapping Algorithms in FPGA

Much effort overlaps in designing different hardware to implement different Simultaneous localization and mapping (SLAM) algorithms. In this brief, a reconfigurable architecture with dedicated instruction sets allows the coprocessor to satisfy the pose estimation of a sample class of the SLAM algorithms, feature-based or learning-based methods, which can be decomposed to basic common operations. Furthermore, a memory-reused strategy in instructions was designed to avoid the demand for temporary memory for complex operations. Finally, two parallel computing cores are implemented to perform matrix operations and special computation about the pose estimation in floating-point and fixed-point arithmetic. These contribute to the low hardware resource usage and memory requirement, as illustrated in the experimental results.

A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol and its Application

The use of application-specific accelerators in data centers has been the state of the art for at least a decade, starting with the availability of General Purpose GPUs achieving higher performance either overall or per watt. In most cases, these accelerators are coupled via PCIe interfaces to the corresponding hosts, which leads to disadvantages in interoperability, scalability and power consumption. As a viable alternative to PCIe-attached FPGA accelerators this paper proposes standalone FPGAs as Network-attached Accelerators (NAAs) . To enable reliable communication for decoupled FPGAs we present an RDMA over Converged Ethernet v2 (RoCEv2) communication stack for high-speed and low-latency data transfer integrated into a hardware framework. For NAAs to be used instead of PCIe coupled FPGAs the framework must provide similar throughput and latency with low resource usage. We show that our RoCEv2 stack is capable of achieving 100 Gb/s throughput with latencies of less than 4μs while using about 10% of the available resources on a mid-range FPGA. To evaluate the energy efficiency of our NAA architecture, we built a demonstrator with 8 NAAs for machine learning based image classification. Based on our measurements, network-attached FPGAs are a great alternative to the more energy-demanding PCIe-attached FPGA accelerators.

Estimation of user activity prior for active user detection in massive machine type communications

To enable massive-scale connectivity with low latency and efficient resource usage for massive machine type communications, the grant free access scheme has been proposed, which allows users to communicate with low signaling overhead and without the need for any prior resource allocation procedure. Due to the sporadic nature of packet transmission and non-orthogonal multiplexing, access points need to perform active user detection (AUD) to identify which users have sent the packets based on the received data. In this paper, we propose an enhanced AUD algorithm, which exploits each user’s activity pattern for detecting active users. We assume that each user randomly sends its own packet with different probability distributions parameterized by the user activity probability (UAP). In our work, such UAPs are inferred from the trajectory of the measurements collected over a certain period of time. Then, the estimated UAPs are incorporated into the compressed sensing-based algorithm for the joint AUD and channel estimation. Using the expectation-maximization algorithm, our method can efficiently find the maximum likelihood estimate of the UAPs for all users. We also present an on-line algorithm that sequentially updates the UAP estimates for each measurement. Our numerical evaluation demonstrates the benefit of the UAP estimation for compressed sensing-based AUD methods.

TORRES: A Resource-Efficient Inference Processor for Binary Convolutional Neural Networks Based on Locality-Aware Operation Skipping

A binary convolutional neural network (BCNN) is a neural network promising to realize analysis of visual imagery in low-cost resource-limited devices. This study presents an efficient inference processor for BCNNs, named TORRES. TORRES performs inference efficiently, skipping operations based on the spatial locality inherent in feature maps. The training process is regularized with the objective of skipping more operations. The microarchitecture is designed to skip operations and generate addresses efficiently with low resource usage. A prototype inference system based on TORRES has been implemented in a 28 nm field-programmable gate array, and its functionality has been verified for practical inference tasks. Implemented with 2.31 K LUTs, TORRES achieves the inference speed of 291.2 GOP/s, exhibiting the resource efficiency of 126.06 MOP/s/LUT. The resource efficiency of TORRES is 1.45 times higher than that of the state-of-the-art work.

Towards the enhancement of AES IP security using hardware obfuscation technique: A practical approach for secure data transmission in IoT

The global market of developing Internet of Things (IoT) devices increases rapidly with improved design goals like cost, energy efficiency, and performance. Unfortunately, the above design goals often come at the expense of security. Illegal access to the network, malicious device control, compromised sensitive information, and theft of personal data are main threats to these devices. As a result, the Advanced Encryption Standard (AES) is sometimes employed to ensure safe transmission and processing of data in IoT Systems. However, tampering, cloning, and reverse engineering are main concerns that impair the computational complexity of the 128-bit AES at the hardware level. Recently hardware obfuscation-based AES has emerged as a comprehensive hardware security approach for reducing threat impacts. The hardware obfuscation schemes efficiently introduce obfuscation keys for AES to conceal its functionality. The Xilinx Vivado 2016.2 software and BASYS-3 FPGA have been used to implement obfuscated AES approaches in this work. The proposed methods have low resource usage in terms of area and power overhead while providing a high level of security in terms of Hamming Distance of 50% and Avalanche Effect of 40% for each obfuscation method. We have also analyzed the probability of success for brute-force attacks for proposed methodologies.

Asynchronous Architecture of Stochastic Computing Spiking Neuron Network

Stochastic computing encodes binary numbers into stochastic pulse sequences in operating, which takes advantages of low power consumption and low resource usage. The application of stochastic computing in the design of spiking neural network (SNN) accelerator is beneficial to realize brain-like operation. In order to realize the low-power edge calculation of neural network, an asynchronous architecture using stochastic computing is designed, which can be used to realize the operation of full connected SNN. Cross array controlled by asynchronous micro-pipeline is implemented to achieve the leaky integrate and fire (LIF) neuron model. In the input layer of SNN, input values are encoded into stochastic pulses, and the synaptic weights and input pulses are calculated through accumulation, and the attenuation of neuron membrane potential value is realized based on logic calculation. The event-driven coding and the transmission of stochastic pulse are controlled by the asynchronous architecture, which can reduce the power consumption of SNN operation; The proposed architecture achieves an operation of SNN with 784 input and 10 output, which is verified on Xilinx KCU116 platform and achieves a peak throughput of 78.4 GSOPS and an energy efficiency of 137.47 GSOPS/W.

IoTSAX: A Dynamic Abstractive Entity Summarization Approach With Approximation and Embedding-Based Reasoning Rules in Publish/Subscribe Systems

Users are interested in entity information and may use paradigms like publish/subscribe systems in Internet of Things (IoT), where entity-centric data comes from multiple sources. The IoT application demands contributed to the data integration and semantic interoperability need while maintaining high usability and low processing system resources usage. Existing approaches dealt with semantic interoperability by using/extending ontologies with strict schemata/semantics and difficult to be updated. Other approaches tackled high usability by providing sensor data abstractions that infer high-level knowledge, but they are either complex for real-time processing or have semantic/syntactic coupling making them nonflexible. Therefore, our key question is: can a dynamic entity summarization system that provides high-level abstractions while ensuring semantic/syntactic decoupling, and low use of processing system resources, be defined? In this article, we address this question by proposing the abstractive publish/subscribe summarization system that provides abstractive summaries of numerical IoT data for user-friendly subscriptions by using IoTSAX, an enhanced symbolic aggregate approximation (SAX) methodology for dynamic IoT environments, and approximate rule-based reasoning by using embedding models. Our results for two use cases, medicine and smart cities, show that although abstraction can be 2 to 3 times slower in latency, it achieves up to 98% reduction in the notifications’ number. IoTSAX outperforms SAX in approximation error up to 2 to 3 times more and in compression space-saving percentage when data redundancy occurs, while it has a similar or better latency and throughput performance. Finally, concept hierarchy-based embedding models can achieve F-scores of up to 0.87 for approximate rule-based reasoning.

FPGA Implementation of an Ant Colony Optimization Based SVM Algorithm for State of Charge Estimation in Li-Ion Batteries

Monitoring the State of Charge (SoC) in battery cells is necessary to avoid damage and to extend battery life. Support Vector Machine (SVM) algorithms and Machine Learning techniques in general can provide real-time SoC estimation without the need to design a cell model. In this work, an SVM was trained by applying an Ant Colony Optimization method. The obtained trained model was 10-fold cross-validated and then designed in Hardware Description Language to be run on FPGA devices, enabling the design of low-cost and compact hardware. Thanks to the choice of a linear SVM kernel, the implemented architecture resulted in low resource usage (about 1.4% of Xilinx Artix7 XC7A100TFPGAG324C FPGA), allowing multiple instances of the SVM SoC estimator model to monitor multiple battery cells or modules, if needed. The ability of the model to maintain its good performance was further verified when applied to a dataset acquired from different driving cycles to the cycle used in the training phase, achieving a Root Mean Square Error of about 1.4%.

AERO: A 1.28 MOP/s/LUT Reconfigurable Inference Processor for Recurrent Neural Networks in a Resource-Limited FPGA

This study presents a resource-efficient reconfigurable inference processor for recurrent neural networks (RNN), named AERO. AERO is programmable to perform inference on RNN models of various types. This was designed based on the instruction-set architecture specializing in processing primitive vector operations that compose the dataflows of RNN models. A versatile vector-processing unit (VPU) was incorporated to perform every vector operation and achieve a high resource efficiency. Aiming at a low resource usage, the multiplication in VPU is carried out on the basis of an approximation scheme. In addition, the activation functions are realized with the reduced tables. We developed a prototype inference system based on AERO using a resource-limited field-programmable gate array, under which the functionality of AERO was verified extensively for inference tasks based on several RNN models of different types. The resource efficiency of AERO was found to be as high as 1.28 MOP/s/LUT, which is 1.3-times higher than the previous state-of-the-art result.

RADSex: A computational workflow to study sex determination using restriction site-associated DNA sequencing data.

The study of sex determination and sex chromosome organization in nonmodel species has long been technically challenging, but new sequencing methodologies now enable precise and high-throughput identification of sex-specific genomic sequences. In particular, restriction site-associated DNA sequencing (RAD-Seq) is being extensively applied to explore sex determination systems in many plant and animal species. However, software specifically designed to search for and visualize sex-biased markers using RAD-Seq data is lacking. Here, we present RADSex, a computational analysis workflow designed to study the genetic basis of sex determination using RAD-Seq data. RADSex is simple to use, requires few computational resources, makes no prior assumptions about the type of sex-determination system or structure of the sex locus, and offers convenient visualization through a dedicated R package. To demonstrate the functionality of RADSex, we re-analysed a published data set of Japanese medaka, Oryzias latipes, where we uncovered a previously unknown Y chromosome polymorphism. We then used RADSex to analyse new RAD-Seq data sets from 15 fish species spanning multiple taxonomic orders. We identified the sex determination system and sex-specific markers in six of these species, five of which had no known sex-markers prior to this study. We show that RADSex greatly facilitates the study of sex determination systems in nonmodel species thanks to its speed of analyses, low resource usage, ease of application and visualization options. Furthermore, our analysis of new data sets from 15 species provides new insights on sex determination in fish.

Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis

A well-known approach for generating custom hardware with high throughput and low resource usage is modulo scheduling, in which the number of clock cycles between successive inputs (the initiation interval, II) can be lower than the latency of the computation. The II is traditionally an integer, but in this paper, we explore the benefits of allowing it to be a rational number. A rational II can be interpreted as the average number of clock cycles between successive inputs. Since the minimum rational II can be less than the minimum integer II, higher throughput is possible; moreover, allowing rational IIs gives more options in a design-space exploration. We formulate rational-II modulo scheduling as an integer linear programming (ILP) problem that is able to find latency-optimal schedules for a fixed rational II. We also propose two heuristic approaches that make rational-II scheduling more feasible: one based on identifying strongly connected components in the data-flow graph, and one based on iteratively relaxing the target II until a solution is found. We have applied our methods to a standard benchmark of hardware designs, and our results demonstrate an average speedup w.r.t. II of 1.24× in 35% of the encountered scheduling problems compared to state-of-the-art formulations.

PRIPRO—Privacy Profiles: User Profiling Management for Smart Environments

Smart environments are pervasive computing systems that provide higher comfort levels on daily routines throughout interactions among smart sensors and embedded computers. The lack of privacy within these interactions can lead to the exposure of sensitive data. We present PRIPRO (PRIvacy PROfiles), a management tool that includes an Android application that acts on the user’s smartphone by allowing or blocking resources according to the context, in order to address this issue. Back-end web server processes and imposes a protocol according to the conditions that the user selected beforehand. The experimental results show that the proposed solution successfully communicates with the Android Device Administration framework, and the device appropriately reacts to the expected set of permissions imposed according to the user’s profile with low response time and resource usage.