Low Resource Usage Research Articles

What horticulture and space exploration can learn from each other: The Mission to Mars initiative in the Netherlands

The horticulture sector in the Netherlands is a global leader due to technological advancements, knowledge of greenhouse cultivation with high productivities and low resource usage, and entrepreneurship. The Netherlands is the second largest exporter of vegetables in the world, and more than half of its land area is used for agriculture with some greenhouse complexes covering 175 acres. However, to retain this leading position, the sector has acknowledged that it needs to keep innovating. To further reduce waste and environmental impact, an innovative production strategy is being developed to support a circular economy: the circular greenhouse. LDE Greenport Hub is an entity of the strategic alliance of the universities of Leiden, Delft and Erasmus and is focused on horticulture scientific research and education in collaboration with major horticulture industry partners (such as sector association Glastuinbouw Nederland). It has initiated ‘Mission to Mars’, a program to boost innovation and development of the circular greenhouse by adopting concepts and technologies from space. Space is inherently focused on circularity because of scarce resources. A good example is the MELiSSA concept of the European Space Agency in which human waste is broken down into nutrients for crops and algae by a series of bioreactors. The crops and algae consequently provide food and oxygen for the crew again. The Mission to Mars program started with a lecture series in the beginning of 2018 at the World Horti Center, a horticulture business and innovation center in Naaldwijk. In seven lectures different aspects of sustainability and circularity were explored together with researchers, students, growers and horticulturists. The lectures covered (1) energy, (2) water, (3) lighting and climate, (4) soil, substrate and plant health, (5) material and energy streams, (6) digitization and automation, and (7) urban and vertical farming. It quickly became clear that not only terrestrial horticulture could benefit from space technologies, but that human space exploration could equally benefit from the technical and tacit knowledge of growers and horticulturists for food production in space. A list of potential research topics was identified. These topics are to be explored in a follow-up ESA Innovation Exchange, together with space technology partner ICE Cubes. The goal is to go beyond the circular greenhouse and demonstrate how space itself can be an environment for plant biology innovation, and hence increase future food security on Earth.

Hardware Design of a Context-Preserving Filter-Reorganized CNN for Super-Resolution

This paper presents a hardware design of a CNN for single image super-resolution (SISR) processing. Very deep convolutional network for image super-resolution (VDSR) is a promising algorithm for SISR generating high-quality images but it is too complex to be implemented in hardware for commercial products. The paper presents a novel hardware design that is applicable to commercial products with low hardware resource usage while avoiding a significant degradation of image quality. The proposed design employs sub-pixel convolution layers to support various scale factors. A context-preserving 1D reorganization scheme is proposed to reduce the number of multipliers. Additional optimization technique is proposed to reduce the internal SRAM to store the input feature map. Thanks to the proposed optimizations along with additional techniques popular in hardware design, the number of multipliers and the size of SRAMs are reduced to 1/118.27 and 1/47.59, respectively, in comparison with a straightforward implementation of VDSR. The proposed CNN hardware synthesized with TSMC 65-nm CMOS technology, and it requires 8153.1K gate counts and 333.1kB SRAM to process a full-HD image. The proposed context-preserving 1D reorganization and memory reduction optimizations are also applicable to denoising and image classification without a significant performance degradation.

Better together: Comparing vulnerability prediction models

Abstract Context Vulnerability Prediction Models (VPMs) are an approach for prioritizing security inspection and testing to find and fix vulnerabilities. VPMs have been created based on a variety of metrics and approaches, yet widespread adoption of VPM usage in practice has not occurred. Knowing which VPMs have strong prediction and which VPMs have low data requirements and resources usage would be useful for practitioners to match VPMs to their project’s needs. The low density of vulnerabilities compared to defects is also an obstacle for practical VPMs. Objective The goal of the paper is to help security practitioners and researchers choose appropriate features for vulnerability prediction through a comparison of Vulnerability Prediction Models. Method We performed replications of VPMs on Mozilla Firefox with 28,750 source code files featuring 271 vulnerabilities using software metrics, text mining, and crash data. We then combined features from each VPM and reran our classifiers. Results We improved the F-score of the best VPM (.20 to 0.28) by combining features from three types of VPMs and using Naive Bayes as the classifier. The strongest features in the combined model were the number of times a file was involved in a crash, the number of outgoing calls from a file, and the string “nullptr”. Conclusion Our results indicate that further work is needed to develop new features for input into classifiers. In addition, new analytic approaches for VPMs are needed for VPMs to be useful in practical situations, due to the low density of vulnerabilities in software (less than 1% for our dataset).

Hardware Friendly Robust Synthetic Basis Feature Descriptor

Finding corresponding image features between two images is often the first step for many computer vision algorithms. This paper introduces an improved synthetic basis feature descriptor algorithm that describes and compares image features in an efficient and discrete manner with rotation and scale invariance. It works by performing a number of similarity tests between the feature region surrounding the feature point and a predetermined number of synthetic basis images to generate a feature descriptor that uniquely describes the feature region. Features in two images are matched by comparing their descriptors. By only storing the similarity of the feature region to each synthetic basis image, the overall storage size is greatly reduced. In short, this new binary feature descriptor is designed to provide high feature matching accuracy with computational simplicity, relatively low resource usage, and a hardware friendly design for real-time vision applications. Experimental results show that our algorithm produces higher precision rates and larger number of correct matches than the original version and other mainstream algorithms and is a good alternative for common computer vision applications. Two applications that often have to cope with scaling and rotation variations are included in this work to demonstrate its performance.

Optimization and Security in Information Retrieval, Extraction, Processing, and Presentation on a Cloud Platform

This paper presents the processing steps needed in order to have a fully functional vertical search engine. Four actions are identified (i.e., retrieval, extraction, presentation, and delivery) and are required to crawl websites, get the product information from the retrieved webpages, process that data, and offer the end-user the possibility of looking for various products. The whole application flow is focused on low resource usage, and especially on the delivery action, which consists of a web application that uses cloud resources and is optimized for cost efficiency. Novel methods for representing the crawl and extraction template, for product index optimizations, and for deploying and storing data in the cloud database are identified and explained. In addition, key aspects are discussed regarding ethics and security in the proposed solution. A practical use-case scenario is also presented, where products are extracted from seven online board and card game retailers. Finally, the potential of the proposed solution is discussed in terms of researching new methods for improving various aspects of the proposed solution in order to increase cost efficiency and scalability.

Digital background calibration algorithm and its FPGA implementation for timing mismatch correction of time-interleaved ADC

Sample time error can degrade the performance of time-interleaved analog to digital converters (TIADCs). A fully digital background algorithm is presented in this paper to estimate and correct the timing mismatch errors between four interleaved channels, together with its hardware implementation. The proposed algorithm provides low computation burden and high performance. It is based on the simplified representation of the coefficients of the Lagrange interpolator. Simulation results show that it can suppress error tones in all of the Nyquist band. Results show that, for a four-channel TIADC with 10-bit resolution, the proposed algorithm improves the signal to noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) by 19.27 dB and 35.2 dB, respectively. This analysis was done for an input signal frequency of $$0.09f_s$$ . In the case of an input signal frequency of $$0.45f_s$$ , an improvement by 33.06 dB and 43.14 dB is respectively achieved in SNDR and SFDR. In addition to the simulation, the algorithm was implemented in hardware for real-time evaluation. The low computational burden of the algorithm allowed an FPGA implementation with a low logic resource usage and a high system clock speed (926.95 MHz for four channel algorithm implementation). Thus, the proposed architecture can be used as a post-processing algorithm in host processors for data acquisition systems to improve the performance of TIADC.

Opportunistic topology control for ad hoc wireless network survivability enhancement based on LIMOS model

Traditional topology controls existed on wireless networks are mostly based on a deterministic link model which only takes the decisive links into consideration. All these algorithms do not utilize the benefit of wide existence of lossy links. In a more realistic environment, lossy links are tremendous. Failure to utilize these links leads to low resource usage and relatively low network survivability. In this paper, we propose a lossy probabilistic network model with Obstacle Shadow awareness ability based on the quasi-UDG Link Model (LIMOS model). On the basis of this model, we design a Lossy Link Aware Opportunistic Topology Control (LOLA-OTC) algorithm which aims to utilize high quality lossy links in order to enhance the network performance. The computational complexity of the LOLA-OTC is O(Δn2 + Δn) and the total message complexity of LOLA-OTC is O(n). We also present performance evaluation results on the energy consumption, packet loss ratio, and network throughput according to different node density settings through extensive simulations under ns2 network simulator. The numerical results demonstrate that the LOLA-OTC can obtain better network performance compared to other non-opportunistic topology control algorithms in most cases.

Digital Biosensing by Foundry-Fabricated Graphene Sensors

The prevailing philosophy in biological testing has been to focus on simple tests with easy to interpret information such as ELISA or lateral flow assays. At the same time, there has been a decades long understanding in device physics and nanotechnology that electrical approaches have the potential to drastically improve the quality, speed, and cost of biological testing provided that computational resources are available to analyze the resulting complex data. This concept can be conceived of as “the internet of biology” in the same way miniaturized electronic sensors have enabled “the internet of things.” It is well established in the nanotechnology literature that techniques such as field effect biosensing are capable of rapid and flexible biological testing. Until now, access to this new technology has been limited to academic researchers focused on bioelectronic devices and their collaborators. Here we show that this capability is retained in an industrially manufactured device, opening access to this technology generally. Access to this type of production opens the door for rapid deployment of nanoelectronic sensors outside the research space. The low power and resource usage of these biosensors enables biotech engineers to gain immediate control over precise biological and environmental data.

Towards Improving Productivity in NMapSecurity Audits

Maintaining an adequate security level in computer infrastructures, like Internet-facing web servers, requires periodic assessment of their vulnerabilities with specialized security tools. nmap is arguably the most popular one, due to its versatility, powerful features, and low resource usage. However, this versatility can turn its usage difficult and error-prone, as it implements a lot of features and reports errors at runtime. This can lead to suboptimal results while designing auditing tasks. This research aims to decrease this complexity by developing a web GUI that favors experimentation, on-demand scans, and provides solutions to several shortcomings detected in the official one. We complemented it with a Domain Specific Language that implements early detection and reporting of syntax, type, and semantic errors when creating audit tasks. Both expand nmap possibilities, creating robust, schedulable, distributable, and portable auditing tasks able to find anomalies analyzing their output. Our initial release shows that the web GUI has been well received by several security related media and professionals. The language can detect and report a wide range of potential errors, substantially increasing the robustness of the created tasks. Therefore, Domain Specific Languages with early detection of type errors turned to be suitable to lower the complexity and expand the usage possibilities of complex tools like nmap.

Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs

A Viterbi decoder is used in many communication receivers to efficiently decode the received signal that has been convolutional encoded in the transmitter. This decoding corrects errors that occur due to noise and other imperfections in the channel and is key to achieve a low bit error rate. If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced soft errors can affect the operation of the Viterbi decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured. This makes the protection of Viterbi decoders implemented on SRAM-based FPGAs an important issue. In this paper, first, fault injection experiments are conducted to study the effects of soft errors on the configuration memory of an SRAM-FPGA implemented Viterbi decoder. Then, an efficient protection technique is proposed and evaluated showing that it can provide an efficient protection with a lower resource usage than the traditional triple modular redundancy approach.

Less Data Same Information for Event-Based Sensors: A Bioinspired Filtering and Data Reduction Algorithm.

Sensors provide data which need to be processed after acquisition to remove noise and extract relevant information. When the sensor is a network node and acquired data are to be transmitted to other nodes (e.g., through Ethernet), the amount of generated data from multiple nodes can overload the communication channel. The reduction of generated data implies the possibility of lower hardware requirements and less power consumption for the hardware devices. This work proposes a filtering algorithm (LDSI—Less Data Same Information) which reduces the generated data from event-based sensors without loss of relevant information. It is a bioinspired filter, i.e., event data are processed using a structure resembling biological neuronal information processing. The filter is fully configurable, from a “transparent mode” to a very restrictive mode. Based on an analysis of configuration parameters, three main configurations are given: weak, medium and restrictive. Using data from a DVS event camera, results for a similarity detection algorithm show that event data can be reduced up to 30% while maintaining the same similarity index when compared to unfiltered data. Data reduction can reach 85% with a penalty of 15% in similarity index compared to the original data. An object tracking algorithm was also used to compare results of the proposed filter with other existing filter. The LDSI filter provides less error (4.86 ± 1.87) when compared to the background activity filter (5.01 ± 1.93). The algorithm was tested under a PC using pre-recorded datasets, and its FPGA implementation was also carried out. A Xilinx Virtex6 FPGA received data from a 128 × 128 DVS camera, applied the LDSI algorithm, created a AER dataflow and sent the data to the PC for data analysis and visualization. The FPGA could run at 177 MHz clock speed with a low resource usage (671 LUT and 40 Block RAM for the whole system), showing real time operation capabilities and very low resource usage. The results show that, using an adequate filter parameter tuning, the relevant information from the scene is kept while fewer events are generated (i.e., fewer generated data).

REMT: A Real-Time End-to-End Media Data Transmission Mechanism in UAV-Aided Networks

In recent years, UAVs have received much attention in both the military and civilian fields for monitoring, emergency relief and searching tasks. UAVs are considered a new technology to obtain data at high altitudes when equipped with sensors. This technology is vital to the success of next-generation monitoring systems, which are expected to be reliable, real-time, efficient and secure. However, due to the bandwidth limitations in UAV-aided networks, the size of the transmitted data is a crucial factor for real-time media data transmission requirements, especially for national defense. To address this issue, in this article, we propose a realtime end-to-end media data transmission mechanism with an unsupervised deep neural network. The proposed mechanism transmutes the media data captured by UAVs into latent codes with a predefined constant size and transmits the codes to the ground console station (GCS) for further reconstruction. We use a real-word dataset containing millions of samples to evaluate the proposed mechanism which achieves a high transmission ratio, low resource usage and good visual quality.

A Hardware-Efficient Synchronization in L-DACS1 for Aeronautical Communications

L-band digital aeronautical communication system type-1 (L-DACS1) is an emerging standard that aims at enhancing air traffic management by transitioning the traditional analog aeronautical communication systems to the superior and highly efficient digital domain. L-DACS1 employs modern and efficient orthogonal frequency-division multiplexing (OFDM) modulation technique to achieve more efficient and higher data rate in comparison to the existing aeronautical communication systems. However, the performance of OFDM systems is very sensitive to synchronization errors such as symbol timing offset (STO) and carrier frequency offset (CFO). STO and CFO estimations are extremely important for maintaining orthogonality among the subcarriers for the retrieval of information. This paper proposes a novel efficient hardware synchronizer for L-DACS1 systems that offers robust performance at low power and low hardware resource usage. Monte Carlo simulations show that the proposed synchronization algorithm provides accurate STO estimation as well as fractional CFO estimation. Implementation of the proposed synchronizer on a widely used field-programmable gate array (FPGA) (Xilinx xc7z020clg484-1) results in a very low hardware usage which consumed 6.5%, 3.7%, and 6.4% of the total number of lookup tables, flip-flops, and digital signal processing blocks, respectively. The dynamic power of the proposed synchronizer is below 1 mW.

Pure FPGA Implementation of an HOG Based Real-Time Pedestrian Detection System.

In this study, we propose a real-time pedestrian detection system using a FPGA with a digital image sensor. Comparing with some prior works, the proposed implementation realizes both the histogram of oriented gradients (HOG) and the trained support vector machine (SVM) classification on a FPGA. Moreover, the implementation does not use any external memory or processors to assist the implementation. Although the implementation implements both the HOG algorithm and the SVM classification in hardware without using any external memory modules and processors, the proposed implementation’s resource utilization of the FPGA is lower than most of the prior art. The main reasons resulting in the lower resource usage are: (1) simplification in the Getting Bin sub-module; (2) distributed writing and two shift registers in the Cell Histogram Generation sub-module; (3) reuse of each sum of the cell histogram in the Block Histogram Normalization sub-module; and (4) regarding a window of the SVM classification as 105 blocks of the SVM classification. Moreover, compared to Dalal and Triggs’s pure software HOG implementation, the proposed implementation‘s average detection rate is just about 4.05% less, but can achieve a much higher frame rate.

FPGA Hardware Implementation of DOA Estimation Algorithm Employing LU Decomposition

In this paper, authors present their work on field-programmable gate array (FPGA) hardware implementation of proposed direction of arrival estimation algorithms employing LU factorization. Both L and U matrices were considered in computing the angle estimates. Hardware implementation was done on a Virtex-5 FPGA and its experimental verification was performed using National Instruments PXI platform which provides hardware modules for data acquisition, RF down-conversion, digitization, etc. A uniform linear array consisting of four antenna elements was deployed at the receiver. LabVIEW FPGA modules with high throughput math functions were used for implementing the proposed algorithms. MATLAB simulations of the proposed algorithms were also performed to validate the efficacy of the proposed algorithms prior to hardware implementation of the same. Both MATLAB simulation and experimental verification establish the superiority of the proposed methods over existing methods reported in the literature, such as QR decomposition-based implementations. FPGA compilation results report low resource usage and faster computation time compared with the QR-based hardware implementation. Performance comparison in terms of estimation accuracy, percentage resource utilization, and processing time is also presented for different data and matrix sizes.

Automating Characterization Deployment in Distributed Data Stream Management Systems

Distributed data stream management systems (DDSMS) are usually composed of upper layer relational query systems (RQS) and lower layer stream processing systems (SPS). When users submit new queries to RQS, a query planner needs to be converted into a directed acyclic graph (DAG) consisting of tasks which are running on SPS. Based on different query requests and data stream properties, SPS need to configure different deployments strategies. However, how to dynamically predict deployment configurations of SPS to ensure the processing throughput and low resource usage is a great challenge. This article presents OrientStream, a framework for automating characterization deployment in DDSMS using incremental machine learning techniques. By introducing the data-level, query plan-level, operator-level, and cluster-level’s four-level feature extraction mechanism, we first use the different query workloads as training sets to predict the resource usage by DDSMS, and select the optimal resource configuration from candidate settings based on the current query requests and stream properties, then migrate the operator state by introducing dynamic reconfiguration. Finally, we validate our approach on the open source SPS–Storm. In view of the application scenarios with long monitoring cycle and non-frequent data fluctuation, experiments show that OrientStream can reduce CPU usage of 8-15 percent and memory usage of 38-48 percent, respectively.

Reducing the number of response time service level objective violations by a cloud‐HPC convergence scheduler

SummaryJob scheduling is an old topic in High‐Performance Computing (HPC), and it is more and more studied in data centers. Large data centers are often split into separate partitions for cloud computing and HPC; each partition normally has its specific scheduler. The possibility of migrating jobs from the HPC partition to the cloud one is a topic widely discussed in the literature. However, job migration from cloud to HPC is a much less explored topic. Nevertheless, such migration may be useful in many situations, in particular when the HPC platform has a low resource usage level, and the cloud usage level is high. A large number of jobs that could migrate from the cloud to the HPC partition may be observed in Google data center workloads. Job scheduling using overbooking strategy is seen as the main reason for the high resource usage level in clouds. However, overbooking can lead to a high rate of rescheduling and job dumping, which potentially causes response time violations. This work shows that HPC platforms can host and execute some cloud jobs with low interference in HPC jobs and a low number of response time violations. We introduce the definition of a cloud‐HPC convergence area and propose a job scheduling strategy for it, aiming at reducing the number of response time violations of cloud jobs without interfering with HPC jobs execution. Our proposal is formally defined and then evaluated in different execution scenarios, using the SimGrid simulation framework, with workload data from production HPC grid. The experimental results show that often, there is a large number of empty areas in the scheduling plan of HPC platforms, which makes it possible to allocate cloud jobs by backfilling. This is due to the sparse HPC job submission pattern and the low resource usage level in some HPC platforms. One performed simulation scenario considered a set of 11K parallel HPC jobs running on a 2560‐processor platform having an average resource usage level of 38.0%. The proposed convergence scheduler succeeded to inject around 267K cloud jobs in the HPC platform, with a response time violation rate under 0.00094% for such jobs, considering 80 processors in the convergence area and no effects on the HPC workload. This experiment considered cloud jobs based on job features of Google public cloud workloads, with a processing time slack factor of 1.25 (which is considered as high priority in the Google cloud SLA—Service Level Agreement). Usually, most cloud jobs show a slack factor higher than 1.25 (most cloud jobs are medium or low priority). The same simulation, repeated with a higher slack factor (4), showed no response time violations.

Evaluation and Comparison of Low FPGA Footprint, Embedded Soft-Core Processors

Abstract The paper presents three embedded soft-core processor architectures, developed by the authors to be easily implementable while yielding low digital resource usage. These architectures will be compared and contrasted between each-other by introducing a special testing method, based on control algorithm implementations. For reference, the same testing and comparison has been implemented on a well established architecture, too, on the Xilinx PicoBlaze processor. Measurement results and application suggestion are given in the concluding section.

Using MaxCompiler for the high level synthesis of trigger algorithms

Firmware for FPGA trigger applications at the CMS experiment is conventionally written using hardware description languages such as Verilog and VHDL. MaxCompiler is an alternative, Java based, tool for developing FPGA applications which uses a higher level of abstraction from the hardware than a hardware description language. An implementation of the jet and energy sum algorithms for the CMS Level-1 calorimeter trigger has been written using MaxCompiler to benchmark against the VHDL implementation in terms of accuracy, latency, resource usage, and code size. A Kalman Filter track fitting algorithm has been developed using MaxCompiler for a proposed CMS Level-1 track trigger for the High-Luminosity LHC upgrade. The design achieves a low resource usage, and has a latency of 187.5 ns per iteration.

On How to Accelerate Iterative Stencil Loops

In high-performance systems, stencil computations play a crucial role as they appear in a variety of different fields of application, ranging from partial differential equation solving, to computer simulation of particles’ interaction, to image processing and computer vision. The computationally intensive nature of those algorithms created the need for solutions to efficiently implement them in order to save both execution time and energy. This, in combination with their regular structure, has justified their widespread study and the proposal of largely different approaches to their optimization. However, most of these works are focused on aggressive compile time optimization, cache locality optimization, and parallelism extraction for the multicore/multiprocessor domain, while fewer works are focused on the exploitation of custom architectures to further exploit the regular structure of Iterative Stencil Loops (ISLs), specifically with the goal of improving power efficiency. This work introduces a methodology to systematically design power-efficient hardware accelerators for the optimal execution of ISL algorithms on Field-programmable Gate Arrays (FPGAs). As part of the methodology, we introduce the notion of Streaming Stencil Time-step (SST), a streaming-based architecture capable of achieving both low resource usage and efficient data reuse thanks to an optimal data buffering strategy, and we introduce a technique called SSTs queuing that is capable of delivering a pseudolinear execution time speedup with constant bandwidth. The methodology has been validated on significant benchmarks on a Virtex-7 FPGA using the Xilinx Vivado suite. Results demonstrate how the efficient usage of the on-chip memory resources realized by an SST allows one to treat problem sizes whose implementation would otherwise not be possible via direct synthesis of the original, unmanipulated code via High-Level Synthesis (HLS). We also show how the SSTs queuing effectively ensures a pseudolinear throughput speedup while consuming constant off-chip bandwidth.