Low-order Bits Research Articles

Modeling of functional language interpreter with metaprogramming

The purpose of the research consists of modeling an interpreter for a functional programming language with metaprogramming capabilities and analyzing ways to implement primitive operators based on macros.Methods. A formal model of a functional language interpreter, which is a subset of Common Lisp, was developed with denotational semantics, which allows you to accurately describe the behavior of the interpreter when calculating language elements such as quoting, accessing variables, sequence of actions, branching, assignment, abstraction, application.Results. Based on denotational semantics, the architecture of a functional language interpreter with metaprogramming capabilities was developed. Numbers, symbols, pairs, strings and arrays were chosen as the basic types of objects. To store objects, a tag architecture was used, where the low-order bits of the object address are always zero, so they can store the object type code and the tag bit. Objects are allocated and freed automatically: a mark and cleanup algorithm is used for garbage collection. Using macros, branching operators, complete and incomplete, selection operator, and block operators of related variables were implemented. Conclusion. As a result of the work, a functional language interpreter with metaprogramming capabilities was implemented. Using macros, primitive operators of condition, selection, and a block of related variables were implemented. Using these operators as an example, it is shown that using metaprogramming, only basic forms and primitives can be built into the interpreter, and the other operators can be implemented using metaprogramming, which makes it possible to simplify and reduce the amount of interpreter code.

A Fast Hardware Pseudorandom Number Generator Based on xoroshiro128

The Graphcore Intelligent Processing Unit contains an original pseudorandom number generator (PRNG) called xoroshiro128aox, based on the F <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -linear generator xoroshiro128. It is designed to be cheap to implement in hardware and provide high-quality statistical randomness. In this paper, we present a rigorous assessment of the generator's quality using standard statistical test suites and compare the results with the fast contemporary PRNGs xoroshiro128+, pcg64 and philox4x32-10. We show that xoroshiro128aox mitigates the known weakness in the lower order bits of xoroshiro128+ with a new ‘AOX’ output function by passing the BigCrush and PractRand suites, but we note that the function has some minor non uniformities. We focus our testing with specific tests for linear artefacts to highlight the weaknesses of both xoroshiro128 PRNGs, but conclude that they are hard to detect, and xoroshiro128aox otherwise provides a good trade off between statistical quality and hardware implementation cost.

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

Partial products of higher radix are approximated by partial product segmentation. The encoder skips few lower order bits to segment the partial products for approximation. For a particular type of approximation, one can have many options of choosing the higher radix for hybrid encoding. However, the selection of higher radix is the key to obtain an optimal approximate hybrid multiplier design. In this paper, we made an in-depth study on radix-64 and radix-256 encoding for 4-bit and 5-bit approximations. Proposed a two-term radix-64 encoding and three-term radix-256 encoding for 4-bit approximation to calculate partial-products with lowest maximum absolute error (MAE). Further, we have proposed a simple rule to select the higher radix for hybrid encoding to obtain an efficient approximate multiplier design. To demonstrate the usefulness of the selection rule, two hybrid encoding schemes named R4R64 and R4R256 are formulated by combining radix-4 separately with proposed two-term radix-64 and three-term radix-256 encoding schemes. Separate multiplier designs are derived using the proposed hybrid encoding. Comparison result shows that both the proposed approximate multipliers have identical output accuracy, but the multiplier design based on proposed hybrid R4R64 encoding is more hardware efficient than the other. Compared with the existing approximate multiplier based on hybrid R4R256 encoding for word-length 12, the proposed multiplier design based on R4R64 hybrid encoding involves nearly 15% less area-delay product (ADP) and a marginal 4% less power-delay-product (PDP), but calculates output with higher accuracy. The 2-D DCT structure using proposed R4R64 multiplier involves 13% lesser ADP and 14% less energy consumption when compared with the 2-D DCT structure based on existing hybrid R4R256 multiplier design and computes reconstructed images with nearly 10dB higher pick signal-to-noise ratio (PSNR).

Structured Dynamic Precision for Deep Neural Networks Quantization

Deep Neural Networks (DNNs) have achieved remarkable success in various Artificial Intelligence applications. Quantization is a critical step in DNNs compression and acceleration for deployment. To further boost DNN execution efficiency, many works explore to leverage the input-dependent redundancy with dynamic quantization for different regions. However, the sensitive regions in the feature map are irregularly distributed, which restricts the real speed up for existing accelerators. To this end, we propose an algorithm-architecture co-design, named Structured Dynamic Precision (SDP). Specifically, we propose a quantization scheme in which the high-order bit part and the low-order bit part of data can be masked independently. And a fixed number of term parts are dynamically selected for computation based on the importance of each term in the group. We also present a hardware design to enable the algorithm efficiently with small overheads, whose inference time mainly scales with the precision proportionally. Evaluation experiments on extensive networks demonstrate that compared to the state-of-the-art dynamic quantization accelerator DRQ, our SDP can achieve 29% performance gain and 51% energy reduction for the same level of model accuracy.

Defending against Adversarial Attacks in Deep Learning with Robust Auxiliary Classifiers Utilizing Bit-plane Slicing

Deep Neural Networks (DNNs) have been widely used in variety of fields with great success. However, recent research indicates that DNNs are susceptible to adversarial attacks, which can easily fool the well-trained DNN-based classifiers without being detected by human eyes. In this article, we propose to integrate the target DNN model with our robust bit-plane classifiers to defend against adversarial attacks. The bit-plane classifiers take bit-planes of input images for convolution, which is motivated by our observation that successful attacks aim to generate imperceptible perturbations, and they mainly affect the low-order bits of pixels in clean images when adding the perturbations. We also propose two metrics, bit-plane perturbation rate and channel modification rate, to further explain the robustness of bit-plane classifiers. We discuss potential adaptive attack and find that our defense can be effective as long as the adversarial examples are qualified. We conduct experiments on dataset CIFAR-10 and GTSRB under white-box attack and black-box attack. The results show that our defense method can effectively increase the average model accuracy from 16.23% to 83.53% under white-box attack and from 40.65% to 88.14% under black-box attack on CIFAR-10 without sacrificing the accuracy of clean images.

A 0.5 V 10 b 3 MS/s 2-Then-1b/Cycle SAR ADC With Digital-Based Time-Domain Reference and Dual-Mode Comparator

This paper presents a low-power asynchronous 10-bit 2-then-1b/cycle successive approximation register (SAR) analog-to-digital converter (ADC). With partial adoption of 2b/cycle mode only for higher-order bit conversions, additional area and power consumption could be minimized while maintaining fast conversion rate. Moreover, unlike the previous 2b/cycle conversion architecture, where two capacitive digital-to-analog converters (C-DACs) and multiple analog comparators are unavoidable, the proposed 2-then-1b/cycle conversion is implemented with only one C-DAC and one analog comparator by utilizing a digital-based time-domain reference. The speed of 1b/cycle conversion for lower-order bits is improved with a dual-mode comparator. With the aforementioned techniques, the prototype 10-bit SAR ADC is fabricated in 65 nm CMOS process. The ADC core occupies an active area of 0.0142 mm2 and consumes power of 3.8 μW at 0.5 V supply voltage and 3 MS/s conversion rate. The SNDR measured at a Nyquist-rate input frequency is 56.41 dB, resulting in a figure of merit (FoM) is 2.33 fJ/c.-s.

High-Speed Counter with Novel LFSR State Extension

This paper presents a high-speed counter architecture associated with novel LFSR state extension. By employing the proposed state extension, an <inline-formula><tex-math notation="LaTeX">$\emph {m}$</tex-math></inline-formula>-bit LFSR counter with <inline-formula><tex-math notation="LaTeX">$(\mathrm{2^{\mathit{m}}}-1)$</tex-math></inline-formula> states is modified to cover <inline-formula><tex-math notation="LaTeX">$\mathrm{2^{\mathit{m}}}$</tex-math></inline-formula> states without degrading the counting rate. Based on the property that only the low-order bits are frequently switched, the proposed counter consists of two sub-counters to achieve a high counting rate and reduce the hardware complexity needed to convert an LFSR state into a binary state. The low-order sub-counter is implemented with the proposed LFSR counter, and the high-order sub-counter is designed by employing the conventional synchronous binary counter. In addition, the implemented counter takes into account the speed degradation caused by the large fan-out of the high-order sub-counter. The proposed counter designed with standard cells operates at 2.08 GHz in a 65 nm CMOS technology, and its counting rate is almost independent of the counter size.

Separable Reversible Data Hiding in Encryption Image with Two-Tuples Coding

Separable Reversible Data Hiding in Encryption Image (RDH-EI) has become widely used in clinical and military applications, social cloud and security surveillance in recent years, contributing significantly to preserving the privacy of digital images. Aiming to address the shortcomings of recent works that directed to achieve high embedding rate by compensating image quality, security, reversible and separable properties, we propose a two-tuples coding method by considering the intrinsic adjacent pixels characteristics of the carrier image, which have a high redundancy between high-order bits. Subsequently, we construct RDH-EI scheme by using high-order bits compression, low-order bits combination, vacancy filling, data embedding and pixel diffusion. Unlike the conventional RDH-EI practices, which have suffered from the deterioration of the original image while embedding additional data, the content owner in our scheme generates the embeddable space in advance, thus lessening the risk of image destruction on the data hider side. The experimental results indicate the effectiveness of our scheme. A ratio of 28.91% effectively compressed the carrier images, and the embedding rate increased to 1.753 bpp with a higher image quality, measured in the PSNR of 45.76 dB.

Low Power Kogge Stone Adder Applied in FIR Filter using Cadance Tool

A maximum width configuration AT is accomplished by post truncation and direct truncation by using a maximum width adder-tree (AT) configuration. The full width Output AT will be truncated by one lower order bit each adder and the lower order bits of the final stage Adder output, when p = dlog2 Ne & N is the size of the Input-Vector, will be truncate in the case of a post-truncation. These two methods are not efficient in design. Carry look forward adder is used for the current process. In this article we propose a new method to obtain truncated feedback of the fixed-width tree type. A probabilistic approximation formula to account for the truncation error is provided. In the AT architecture suggested we have used Kogge stone adder to approximate the output with almost exactly the same precision as the AT fixed-width post-truncation, with the best accuracy in the current AT fixed-width. And in the FIR filter we enforce the current process. Walsh-Hadamard also noted that, based on its proposed fixed width architecture AT, transforming higher-textured images of higher PSNR and moderate textures with approximately the same PSNR that were obtained using current PSNR models, reconstructing images with higher high noise ratio (PSNR). The proposed design provides a further gain, much as with information, to optimise additional blocks that occur in an upstream adder tree (AT) complex architecture.

A Novel Image Encryption Algorithm Based on Chaotic Sequences and Cross-Diffusion of Bits

To protect image information security, we propose an encryption algorithm based on chaotic sequences and bits' cross-diffusion. First, two chaotic sequences are generated by two-dimensional logic-sine coupling mapping, and the original image is scrambled with the two sequences. Secondly, the scrambled image is transformed into a one-dimensional sequence, and the low-order bits between every two pixels are fused to change the detailed information of the image, improved the ability to resist differential attacks. Finally, chaotic sequences are generated by iterative logical mapping to perform pixel replacement and ciphertext diffusion. The known plaintext attack can be effectively resisted because of the stochastic combination of diffusion scheme and chaotic sequence. It also has a significant effect on resisting differential attack. Take Lena image as an example, NPCR and UACI can reach 99.6063% and 33.4477%, respectively, which are very close to the ideal value. The encryption scheme has good key sensitivity and strong ability to resist statistical attacks, which shows that the algorithm has adequate security.

The complexity of computing (almost) orthogonal matrices with ε-copies of the Fourier transform

The complexity of computing the Fourier transform is a longstanding open problem. Very recently, Ailon (2013, 2014, 2015) showed in a collection of papers that, roughly speaking, a speedup of the Fourier transform computation implies numerical ill-condition. The papers also quantify this tradeoff. The main method for proving these results is via a potential function called quasi-entropy, reminiscent of Shannon entropy. The quasi-entropy method opens new doors to understanding the computational complexity of the important Fourier transformation. However, it suffers from various obvious limitations. This paper is motivated by one such limitation, related to the computation of near-orthogonal matrices that have the Fourier transform ‘hidden’ in low-order bits. While partly overcoming this limitation, the paper sheds light on new interesting, open problems on the intersection of computational complexity and group theory. The paper also explains why this research direction, if fruitful, has a chance of solving much bigger questions about the complexity of the Fourier transform.

Channel of Measurement and Indication of 220 Voltage in the Device «Quality-E1»

At the V.M. Glushkov Institute of Cybernetics the “Yakist-E1” – electric power quality measuring device, was developed. The device uses new method and structure of a quality determination, and is based on calculating the deviations from the nominal values of voltage and frequency values. The methodical error of level quantization for a 10-bit ADC is ± 0.1%. To achieve an approximation error of ± 0.1%, it is necessary to measure the voltage near the amplitude value after 170 μs. The channel for voltage measuring in the device consists of a voltage transformer, a high-precision resistive divider that scales and biases the input voltage, a reference voltage source (VREF) and an ADC, which built into the microcontroller. The device “Yakist-E1” uses an 8-bit microcontroller type C8051F320, which has a 10-bit ADC with an input signal range from 0 to 2.5 V. The output voltage of the VREF from the chip to the controller chip can vary from 2.38 V to 2.5 V. In addition, different transformer sensors may have different transfer characteristics, which may be non-linear. Therefore, to indicate the values of the measured voltage on the alphanumeric indicator, a piecewise linear approximation of the results of measuring the ADC is used. The transfer and temperature characteristics of the voltage transformer were measured for forward and reverse passages, and, according to the results, was discovered that the temperature error is very small and practically does not affect the accuracy of the sensor and the sensor has hysteresis, the calculated errors do not exceed ± 1%. All this errors were corrected. To determine the deviation of the amplitude value from the nominal value, only 8 low-order bits of the ADC are used. This trick grants that ADC result can be processed by a single command of the microcontroller, which increases processing speed of the channel.

Optimal steganography with blind detection based on Bayesian optimization algorithm

An optimal steganography method is provided to embed the secret data into the low-order bits of host pixels. The main idea of the proposed method is that before the embedding process, the secret data are mapped to the optimal values using Bayesian optimization algorithm (along with introducing a novel mutation operator), in order to reduce the mean square error (MSE) and also maintain the structural similarity between the images before and after embedding (i.e., preserving the visual quality of the embedded-image). Then, the mapped data are embedded into the low-order bits of host pixels using modulus function and a systematic and reversible algorithm. Since the proposed method is able to embed data into more significant bits, it has enhanced the payload, while preserving the visual quality of the image. Extraction of data from the host image is possible without requiring the original image. The simulation results show that the proposed algorithm can lead to a minimum loss in MSE criterion and also a minimal reduction in visual quality of the image in terms of diagnostic criteria of the human eye, whereas there is no limitation on the improvement of payload, in comparison with other methods.

A Simple and Efficient IQ Data Compression Method Based on Latency, EVM, and Compression Ratio Analysis

Latency, error vector magnitude (EVM) and compression ratio (CR) are performance evaluation factors of IQ data compression. The purposes of IQ data compression are to minimize the latency, EVM and to maximize the CR. However, there is a tradeoff between them. In this paper, based on the evaluation factors, we analyze existing IQ data compression schemes and propose a simple and efficient method from the analyzed results. The proposed method is composed of partial cyclic prefix and cyclic suffix insertion, $K/L$ decimation, low-order bits removal, and partial Huffman code. It presents the techniques to minimize the EVM caused by $K/L$ decimation and to optimize the number of removable low bits and available Huffman encoding bits based on the average signal power and desired EVM. The proposed method can achieve the CR of 4 times or more in about 2% EVM for the LTE downlink and uplink. The simulation results show that the proposed method is applicable to SIMO and MIMO environments.

A three stage integrated denoising approach for grey scale images

Restoration of the images contaminated with Additive White Gaussian Noise (AWGN) is a fundamental operation at the interface of statistical and functional analysis. It is an extremely exigent job to design a noise suppression algorithm with edge and feature detail preservation owing to random manifestation of the noise amongst the pixels. In spite of documentation of the sophisticated denoising algorithms in literature, a desired amount of applicability is not achieved as they leave residual noise, create artifacts and remove fine structures. In this paper we propose an integrated image denoising algorithm which exploits the bit plane slicing based image decomposition approach for residual noise removal especially at higher noise levels. The intuitive idea of segregation of noise in decomposed bit planes and selective criterion of denoising lower order bit planes with adaptive bitonic filtering is able to preserve feature details while showing strong denoising performance. Experimental analysis shows that the proposed methodology gives considerable results at low noise values and outperforms other existing techniques at higher noise values both in terms of qualitative and quantitative performance.

Flexible Hybrid PAM2/4 for Fidelity Optimization in Digital Mobile Fronthaul

Four-level pulse amplitude modulation (PAM4) has been considered as a low-cost modulation format for capacity upgrade in digital mobile fronthaul; however, the bit error ratio increases due to the reduced Euclidean distance. In this letter, a novel scheme is proposed to suppress bit-error-induced error vector magnitude (EVM) distortion upon radio signal in PAM4-based fronthaul. The scheme is realized by pairing one high-order bit and one low-order bit onto one PAM4 symbol and setting a portion of low-order bits to “0.” As a result, sample bits with high priority are delivered by PAM2 symbols with small error probability, and sample bits with low priority are transmitted by PAM4 signal with high spectral efficiency. Without any modification of the hardware, the proportion between PAM2 and PAM4 can be flexibly adjusted according to the quality of optical link. Experiments validate that, under respective optimal PAM2/4 proportion, EVM of long term evolution-advanced like radio signal decreases by at least 20 dB, and up to 1024-quadratic-amplitude modulation can be supported.

CMOS based Power Efficient Digital Comparator with Parallel Prefix Tree Structure

A 128-Bit Digital Comparator is designed with Digital Complementary Metal Oxide Semiconductor (CMOS) logic, with the use of Parallel Prefix Tree Structure [1] technique. The comparison is performed on Most Significant Bit (MSB) to the Least Significant Bit (LSB). The comparison for the lower order bits carried out only when the MSBs are equal. This technique results in Optimized Power consumption and improved speed of operation. To make the circuit regular, the design is made using only CMOS logic gates. Transmission gates were used in the existing design and are replaced with the simple AND gates. This 128-Bit comparator is designed using Cadence TSMC 0.18µm technology and optimized the Power dissipation to 0.28mW and with a Delay of 0.87μs.

High Speed Error Tolerant Adder for Multimedia Applications

In this paper, a 1-bit modified full adder (MFA) cell is proposed. This eliminates the carry propagation during the addition by allowing errors in the carry bit. Using the proposed MFA, a 16-bit high speed error tolerant adder (HSETA) circuit is designed with conventional carry select adder (CSLA) structure for higher order bits and MFA based structure for lower order bits. The performance of HSETA is compared with existing adders in terms of accuracy, gate count, delay and power dissipation. The gate count of the HSETA is reduced by 23% and speed is improved by 43% compared to a conventional 16-bit adder structure. Further, implementation on FPGA Spartan 6 shows that HSETA uses 53% fewer LUT and 63% fewer slices compared to the conventional adder. Image blending application is used to evaluate the performance of the HSETA. In addition, to perform extensive error analysis, an analytical model is developed for HSETA and tested for varying bit widths and input probabilities. The analytical model is validated through simulation.

Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

In this paper, we present a regular partial product array (PPA) for radix-8 Booth multiplication by removing the extra row with a small overhead complexity. A radix-8 multiplier design is proposed based on the regular PPA which offers a saving of 10.7 % area-delay product (ADP) over the existing radix-8 multiplier design. The n lower-order bits of 2n bit output of full-width multiplier are truncated to have a fixed-width multiplier with low truncation error, where n is the operand bit-width. Few redundant logic operations are created in the adder unit when n lower-order bits of 2n-bit multiplier output are truncated. A specific design is necessary as the modern synthesis tools partially remove these redundant logics. We present an optimized adder unit design after removing redundant logic for post-truncated fixed-width radix-8 Booth multiplier. Comparison result shows that the proposed post-truncated fixed-width multiplier design offers nearly 20.7 % ADP and 18.3 % power saving over the existing radix-8 design optimized by the Synopsys Design Compiler when 2n-bit output is post-truncated to n-bit. More often, multipliers are used for multiplication of constant. The value of the constant may be fixed or could be changed during run-time by the user. The multiplier that multiplies fixed constant is referred to fixed-constant multiplier and that multiplies constant which changes during run-time is referred to generic-constant multiplier. Both radix-4 and radix-8 Booth multiplier designs easily can be configured for a generic-constant multiplier. However, radix-8 multiplier design offers to save some area and delay when configured for constant multiplication, while the radix-4 multiplier design does not have this feature. We find that the proposed 12-bit full-width and fixed-width radix-8 generic-constant multiplier designs, respectively, involve 19.4 and 24.7 % less ADP than the existing radix-4 full-width and post-truncated multiplier designs configured for constant multiplication. The existing block-based lifting 2-D DWT structure is synthesized using the proposed radix-8 generic-constant fixed-width multiplier design to demonstrate the effectiveness of proposed multiplier designs. We find that the existing lifting 2-D DWT structure of block size 16 and word length 12 offers 19.3 % ADP saving and 11.5 % power saving when the constant multipliers are implemented using the proposed radix-8 multiplier design instead of the existing radix-4 multiplier design.

A Simple Approach to Design a Binary Coded Absolute Shaft Encoder

In this paper, an optical type absolute shaft encoder coding pattern is presented. Compared with the conventional binary or gray code pattern resolution ( ${2}^{n}$ ), the proposed code exhibits two times more resolution ( $2^{n^{2}}$ ). Even, to represent high density positional information of rotating object, it is required very less number of tracks. This pattern sequence is based on $n$ -by-2 matrices of binary codes where consecutive two columns of each code represented as high–low order bits. To retrieve the encoded position from these coding patterns, an extra pulse track was added at the outside of coded tracks. Moreover, it was used for providing a synchronized clock pulse into a simple photodetector-based sequential logic circuitry; it is the decoding unit of this encoder. Thus, depending on these synchronized pulses, the proposed encoder is able to provide error free positional information for a high-speed rotating object. Eventually, in order to prove this concept, a prototype is designed and tested, where a satisfactory performance was achieved.