Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

Abstract

In this paper, we present a regular partial product array (PPA) for radix-8 Booth multiplication by removing the extra row with a small overhead complexity. A radix-8 multiplier design is proposed based on the regular PPA which offers a saving of 10.7 % area-delay product (ADP) over the existing radix-8 multiplier design. The n lower-order bits of 2n bit output of full-width multiplier are truncated to have a fixed-width multiplier with low truncation error, where n is the operand bit-width. Few redundant logic operations are created in the adder unit when n lower-order bits of 2n-bit multiplier output are truncated. A specific design is necessary as the modern synthesis tools partially remove these redundant logics. We present an optimized adder unit design after removing redundant logic for post-truncated fixed-width radix-8 Booth multiplier. Comparison result shows that the proposed post-truncated fixed-width multiplier design offers nearly 20.7 % ADP and 18.3 % power saving over the existing radix-8 design optimized by the Synopsys Design Compiler when 2n-bit output is post-truncated to n-bit. More often, multipliers are used for multiplication of constant. The value of the constant may be fixed or could be changed during run-time by the user. The multiplier that multiplies fixed constant is referred to fixed-constant multiplier and that multiplies constant which changes during run-time is referred to generic-constant multiplier. Both radix-4 and radix-8 Booth multiplier designs easily can be configured for a generic-constant multiplier. However, radix-8 multiplier design offers to save some area and delay when configured for constant multiplication, while the radix-4 multiplier design does not have this feature. We find that the proposed 12-bit full-width and fixed-width radix-8 generic-constant multiplier designs, respectively, involve 19.4 and 24.7 % less ADP than the existing radix-4 full-width and post-truncated multiplier designs configured for constant multiplication. The existing block-based lifting 2-D DWT structure is synthesized using the proposed radix-8 generic-constant fixed-width multiplier design to demonstrate the effectiveness of proposed multiplier designs. We find that the existing lifting 2-D DWT structure of block size 16 and word length 12 offers 19.3 % ADP saving and 11.5 % power saving when the constant multipliers are implemented using the proposed radix-8 multiplier design instead of the existing radix-4 multiplier design.