Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

Abstract

Partial products of higher radix are approximated by partial product segmentation. The encoder skips few lower order bits to segment the partial products for approximation. For a particular type of approximation, one can have many options of choosing the higher radix for hybrid encoding. However, the selection of higher radix is the key to obtain an optimal approximate hybrid multiplier design. In this paper, we made an in-depth study on radix-64 and radix-256 encoding for 4-bit and 5-bit approximations. Proposed a two-term radix-64 encoding and three-term radix-256 encoding for 4-bit approximation to calculate partial-products with lowest maximum absolute error (MAE). Further, we have proposed a simple rule to select the higher radix for hybrid encoding to obtain an efficient approximate multiplier design. To demonstrate the usefulness of the selection rule, two hybrid encoding schemes named R4R64 and R4R256 are formulated by combining radix-4 separately with proposed two-term radix-64 and three-term radix-256 encoding schemes. Separate multiplier designs are derived using the proposed hybrid encoding. Comparison result shows that both the proposed approximate multipliers have identical output accuracy, but the multiplier design based on proposed hybrid R4R64 encoding is more hardware efficient than the other. Compared with the existing approximate multiplier based on hybrid R4R256 encoding for word-length 12, the proposed multiplier design based on R4R64 hybrid encoding involves nearly 15% less area-delay product (ADP) and a marginal 4% less power-delay-product (PDP), but calculates output with higher accuracy. The 2-D DCT structure using proposed R4R64 multiplier involves 13% lesser ADP and 14% less energy consumption when compared with the 2-D DCT structure based on existing hybrid R4R256 multiplier design and computes reconstructed images with nearly 10dB higher pick signal-to-noise ratio (PSNR).