Priority-based SRAM design

Abstract

In memory design, people have conventionally assumed that all bit-cells have same importances and hence, made many efforts to obtain memory free from bit-cell failures. However, such an assumption may not be true in video applications such as H.264 and MPEG-4. Here, higher order bits of luminance pixels can be considered more critical compared to lower order bits. It is due to the fact that human visual system is mostly sensitive to the higher order bits. To efficiently exploit this characteristic of video applications, we explore the possibility of priority-based SRAM design in this work. We present a hybrid SRAM array as an example of the priority-based SRAM design. Here, the higher order bits are stored in robust 8T bit-cells while the lower order bits are stored in conventional 6T bit-cells. This facilitates aggressive scaling of supply voltage in memory as the important luma bits, stored in 8T bit-cells, remain relatively unaffected by voltage scaling. The not-so-important lower order luma bits, stored in 6T bit-cells, if affected, contribute insignificantly to the overall degradation in output video quality. Simulation results show that under iso-area condition, we can obtain at least 32% power savings in the hybrid memory array compared to the conventional 6T SRAM array.