Low On-state Voltage Drop Research Articles

Noval carrier accumulation reverse-conducting lateral insulated gate bipolar transistor

Reverse-conducting lateral insulated gate bipolar transistor (RC-LIGBT) with freewheeling diode integrated in the body by introducing n<sup>+</sup> anode can realize the reverse conduction and optimize the turn-off characteristics of the device, which is a promising device in a power integrated circuit. In this work, a novel RC-LIGBT with electron-controlled gate (EG) and separated short-anode (SSA) is proposed and investigated by TCAD simulation, which can achieve low on-state voltage drop (<i>V</i><sub>on</sub>) and low turn-off loss (<i>E</i><sub>off</sub>) at the same time. The EG structure of p-n-n<sup>+</sup>-p (p<sup>+</sup> region/n-type silicon region/n-type barrier layer/p<sup>+</sup> region) is adopted, the gate electrode and anode electrode are connected by the EG structure. In the forward conduction state, a high-density electron accumulation layer is formed on the surface of the drift region by EG structure, which greatly reduces the <i>V</i><sub>on</sub> of the device. At the same time, the use of the SSA structure can also optimize the <i>E</i><sub>off</sub> of the device by forming an additional electron extraction channel. In addition, based on the EG structure, a low-doping p-drift can be combined with the SSA structure to simply achieve reverse-conduction and snapback-free characteristics. Furthermore, the EG structure and the SSA structure can complement each other. On the one hand, the high-density electron accumulation layer formed by EG structure compensates for the weakened conductance modulation effect caused by the SSA structure. On the other hand, the electron extraction channel of the SSA structure enables a large number of accumulated electrons to be removed quickly. The simulation results show that the proposed device has an excellent trade-off relationship between <i>V</i><sub>on</sub> and <i>E</i><sub>off</sub>, specifically, <i>V</i><sub>on</sub> is 1.16V, which is 55% lower than that of SSA LIGBT, and <i>E</i><sub>off</sub> is 0.099 mJ/cm<sup>2</sup>, which is 38.5% and 94.7% lower than that of SSA LIGBT and conventional LIGBT, respectively.

Structure and the Thermal Management of a 3-D Silicon Carbide MOSFET Module

Silicon carbide (SiC) device has higher switching frequency, higher breakdown voltage, and lower on-state voltage drop, which makes it subversive potential in the high power density applications. However, the traditional packaging structure cannot cope with the high power density of SiC devices, so the existing commercial SiC power module can only be used in derating applications. This paper proposed a 3-D packaging design method for high power density MOSFET power module, in which the cooling system is integrated inside the module to reduce the thermal resistance and the temperature difference of the SiC MOSFET chips. At the same time, the heat dissipation process of the new structure is modeled and analyzed, and the accuracy of the model is proved by experiment and simulation.

Multi-Level Multi-Input Converter for Hybrid Renewable Energy Generators

A three-phase multi-level multi-input power converter topology is presented for grid-connected applications. It encompasses a three-phase transformer that is operated on the primary side in an open-end winding configuration. Thus, the primary winding is supplied on one side by a three-phase N-level neutral point clamped inverter and, on the other side, by an auxiliary two-level inverter. A key feature of the proposed approach is that the N-level inverter is able to perform independent management of N − 1 input power sources, thus avoiding the need for additional dc/dc power converters in hybrid multi-source systems. Moreover, it can manage an energy storage system connected to the dc-bus of the two-level inverter. The N-level inverter operates at a low switching frequency and can be equipped with very low on-state voltage drop Insulated-Gate Bipolar Transistor (IGBT) devices, while the auxiliary inverter is instead operated at low voltage according to a conventional high-frequency two-level Pulse Width Modulation (PWM) technique and can be equipped with very low on-state resistance Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) devices. Simulations and experimental results confirm the effectiveness of the proposed approach and its good performance in terms of grid current harmonic content and overall efficiency.

1.2 kV, 10 A, 4H-SiC Bi-Directional Field Effect Transistor (BiDFET) with Low On-State Voltage Drop

Bidirectional power switches are used in matrix-or cyclo-converters and in multistage inverter circuits to facilitate high-frequency AC-to-AC conversion. A new 1.2 kV bidirectional MOSFET (BiDFET) with low on-resistance is achieved and demonstrated using two discrete SiC power MOSFET bare die chips, packaged within a four-terminal custom-designed module. Static and dynamic characterization has been carried out to inspect the on-state and switching behaviour of the BiDFET. The BiDFET is shown to have a low forward voltage drop of 0.6 V at a current of 10 A, which is more than 2.5x smaller than previous Si IGBT and SiC MOSFET based bidirectional switch implementations.

Simulation Study on Dynamic and Static Characteristics of Novel SiC Gate-Controlled Bipolar-Field-Effect Composite Transistor

In this article, a novel bipolar-field-effect composite power transistor, called SiC GCBT (Silicon Carbide Gate-Controlled Bipolar-field-effect Composite Transistor) is presented and studied. The structure is characterized by the use of the base-gate short connection mode, instead of the conventional base-source short connection mode in SiC Vertical Double-diffusion MOSFET (VDMOS). It found that the device can obviously improve many problems of SiC Insulated Gate Bipolar transistor (IGBT) caused by the p-type substrates and eliminate the latch-up effect, having very bright prospects in high power and low frequency applications. The dynamic and static characteristics of the SiC GCBT are studied in detail and compared with SiC VDMOS, SiC IGBT and Si IGBT. Through comparative studies, the analysis results indicate that SiC GCBT has superior static characteristics, including a higher breakdown voltage, a relatively smaller threshold voltage (2.98V) and lower on-state voltage drop, and a much larger on-state current which is 28% higher than that of Si IGBT and 71% higher than that of SiC IGBT. In terms of dynamic characteristics, SiC GCBT has the shortest turn-on time, and the turn-off characteristics of the device are also improved compared with SiC and Si IGBT.

Enhancing Short Circuit Capability of 1.2-kV Si IGBT Using a Gate-Source Shorted Si Depletion Mode MOSFET in Series With the Emitter

Short-circuit (SC) capability is a critical requirement for power switches in modern power electronics applications. A tradeoff between on-state voltage drop, switching loss, and SC capability of insulated gate bipolar transistors (IGBTs) is performed by manufacturers. In general, IGBTs optimized with low on-state voltage have poor SC capability compared with those with good SC capability. In this report, a novel method is described to improve the SC capability of IGBTs optimized with low on-state voltage drop by using a gate-source-shorted Si depletion-mode (DM) mosfet connected in series with the emitter. A seven-fold increase in the SC capability of commercially available 1.2-kV IGBTs was achieved at high dc bus voltages with minimal impact on on-state and switching loss performance. The proposed method also provides a sensing voltage signal at the drain of the Si DM- mosfet , which can be used to monitor the on-state current magnitude and to detect SC fault conditions.

Bipolar AC Switch for Specific Mains Applications: Design, Realization, and Characterization

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$ ). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations.

A High Bidirectional Blocking Capability Insulated-Gate Bipolar Transistor With Ultralow Loss

A novel high bidirectional blocking capability and ultralow loss insulated-gate bipolar transistor with a shorted collector field plate (SCFP) and field stop (FS) layers [SCFP FS reverse blocking (RB)-IGBT] is proposed and its mechanism is investigated by simulations. The device features an SCFP coupled with discontinued N2 layers and an N1 layer as FS layers. First, in the RB process, the SCFP assists in depleting the N2 layers and mergers the depletion boundary, thus, the depletion boundary could easily expand in the lightly doping n-drift region and is stopped by the N1 layer together with trenches, ensuring a high reverse breakdown voltage (BV $_{R}$ ). Second, the trenches are beneficial to shield the high electric field around the P-body/N1 junction (J1) even in condition of a high doping N1, without penalty in forward breakdown voltage (BV $_{F}$ ). Note that a high doping N1 is constructive to obtain a high BV $_{R}$ and low ON-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) owing to the enhanced carrier stored effect. Third, the device exhibits a low turn-OFF loss ( ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ ) since an electron accumulation layer is formed along the SCFP to extract electrons rapidly. The SCFP FS RB-IGBT realizes bidirectional blocking capability ≥800 V and ${E}_{ \mathrm{\scriptscriptstyle OFF}}~49$ % and 67.2% lower than those of bidirectional electric field enhanced FS RB-IGBT and non-punch-through RB-IGBT, respectively.

Design and Manufacturing of 1200V SiC JBS Diodes with Low On-State Voltage Drop and Reverse Blocking Leakage Current

This paper presents the design and fabrication of 1200V-rated SiC JBS diodes in a manufacturing environment. Various designs of p+-grids and edge termination structures were proposed and fabricated on 6-inch SiC substrates. Experimental results show that deeper p+ n junctions are necessary to reduce the leakage current in blocking mode of operation. It was also demonstrated that the hybrid-JTE edge termination structure is very efficient to provide a near-ideal breakdown voltage. Ti and Ni Schottky metals were compared with respect to forward voltage drops and reverse blocking behaviors at high temperatures up to 200 °C.

Simulation Study of a Novel Snapback-Free and Low Turn-Off Loss Reverse-Conducting IGBT With Controllable Trench Gate

A novel ultra-fast snapback-free controllable trench gate (CTG) reverse-conducting insulated gate bipolar transistor (RC-IGBT) is proposed and investigated by simulation. It features a CTG in the collector side and a bias voltage ( ${V}_{\text {RC}}$ ) is applied between the CTG and collector electrode. In the forward conduction state with ${V}_{{\text {RC}}} , a high-density hole inversion layer is formed around the CTG. The CTG acts as not only a folded controllable hole injector to enhance the hole injection efficiency, but also an electron barrier to increase the distributed resistance. The CTG RC-IGBT achieves a low on-state voltage drop ( ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) and snapback-free with a small cell pitch. In the blocking state with ${V}_{\text {RC}} > {0}$ , an electron accumulation layer is formed around the CTG. The electron layer together with the CTG acts as an equivalent N-buffer layer to stop the electric field and support high breakdown voltage. During turn-off, the CTG RC-IGBT behaves like a unipolar device without long tail current because the hole injection is deactivated by properly switching the ${V}_{\text {RC}}$ . Compared with conventional RC-IGBT, the proposed device decreases the ${V}_{\text {on}}$ and turn-off energy loss ( ${E}_{\text{off}}$ ) by 34% and 74%, respectively, under the load current of 100 A/cm2 and bus voltage of 600 V.

Low-Loss SOI-LIGBT With Triple Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) and near the collector side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> ) are shallower than that of the trench (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">M</sub> ) located in the silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> ) in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">E</sub> , resulting in a lower on-state voltage drop (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ). In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">C</sub> and N-buffer region (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) is reduced from 9 μm for the DDOT SOI-LIGBT to 5 μm for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss (E <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) 36.1% lower than the DDOT SOI-LIGBT at the same V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> of 1.53 V.

Investigation on Self-Adjust Conductivity Modulation SOI-LIGBT Structure (SCM-LIGBT) for Monolithic High-Voltage IC

A novel composite device structure named self-adjust conductivity modulation lateral insulated gate bipolar transistor (SCM-LIGBT), including normal LIGBT region (NLT region), the EM-nMOS region (ENM region), and the series diode region (DIO region), is proposed in this paper. By adding the enhanced-mode nMOS region and the series diodes region, the parasitic NPN transistor (NPN) bipolar structure in the normal LIGBT structure can be triggered in on-state and the conductivity modulation is dramatically enhanced, which leads to the improvement on the current capability and the forward voltage. In addition, due to the base voltage of the parasitic NPN bipolar structure in the proposed device can be clamped at the forward threshold of the series diodes, therefore the latch-up issues can be immunized to guarantee the forward-biased safe operating area. Numerous simulations and measurements are presented to investigate the electrical characteristics of the proposed structure. The length of the fabrication SCM-LIGBT is $78.5~\mu \text{m}$ , and the width of the DIO and NLT is 830 $\mu \text{m}$ , while the width of the ENM is $4100~\mu \text{m}$ . The results demonstrate that the proposed SCM-LIGBT achieves a high-current capability ( ${J}_{A})$ of 2428 A/cm2 at ${V}_{G}= 10$ V, a low on-state voltage drop of 1.15 V at ${J}_{A}= 150$ A/cm2 with its breakdown voltage of 590 V.

Low-Loss SOI-LIGBT With Dual Deep-Oxide Trenches

A novel 500-V silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) is proposed for the first time in this paper. The device features triple deep-oxide trenches (TDOT) arranged in the drift region. The depths of the trenches near the emitter side ( ${T}_{\textit {E}})$ and near the collector side ( ${T}_{\textit {C}})$ are shallower than that of the trench ( ${T}_{\textit {M}})$ located in the silicon region between ${T}_{\textit {E}}$ and $T_{\textit {C}}$ . Compared with a reported SOI-LIGBT with dual deep-oxide trenches (DDOT), the shallow trench near the emitter side ( ${T}_{\textit {E}})$ in the proposed TDOT SOI-LIGBT alleviates the JFET effect between the P-body region and ${T}_{\textit {E}}$ , resulting in a lower on-state voltage drop ( ${V} _\mathrm{on})$ . In the off-state, the electric potential sustained by the TDOT is higher than that of the DDOT. At the same breakdown voltage of 560 V, the length of silicon region between $T_{C}$ and N-buffer region ( ${L} _{2})$ is reduced from $9~\mu \text{m}$ for the DDOT SOI-LIGBT to $5~\mu \text{m}$ for the proposed TDOT SOI-LIGBT, indicating a smaller number of stored carries at the collector side and thereby a faster turn-off in the proposed TDOT SOI-LIGBT. The experiments demonstrate that the proposed TDOT SOI-LIGBT achieves turn-off loss ( $\text{E}_{\text {OFF}})~36.1$ % lower than the DDOT SOI-LIGBT at the same ${V}_{\mathrm{on}}$ of 1.53 V.

A U-Shaped Channel SOI-LIGBT With Dual Trenches

This paper proposes a U-shaped channel silicon-on-insulator lateral insulated gate bipolar transistor (SOI-LIGBT) with dual trenches to reduce the turn-off loss while keep the low ON-state voltage drop. The device features a U-shaped gate trench (G1) and a U-shaped hole-barrier trench (G2). By introducing the dual trenches, enhanced carrier stored effect at the emitter side, more uniform carrier distribution in the drift region, and low carrier density at the collector are realized, resulting in decreases of ON-state voltage drop ( ${V}_{\mathrm{\scriptscriptstyle ON}}$ ) and turn-OFF loss ( ${E}_{\mathrm{\scriptscriptstyle OFF}})$ . The proposed SOI-LIGBT offers an ${E}_{\mathrm{\scriptscriptstyle OFF}}~52.3$ % lower than the conventional planar-gate U-shaped channel SOI-LIGBT at the same ${V}_{\mathrm{\scriptscriptstyle ON}}$ of 1.22 V. Moreover, the proposed SOI-LIGBT exhibits a latch-up free characteristic at the current density larger than 1200 A/cm2.

4H-SiC trench IGBT with lower on-state voltage drop

In this paper, a new 4H-SiC trench-gate IGBT structure incorporated a P+ shielding region in the emitter side is proposed in order to reduce the on-state voltage drop. Through the 2-D ATLAS simulation, the characteristics of the proposed structure are investigated and compared with the conventional structure. The simulation results indicate that the proposed structure exhibits an improvement in the following. Firstly, the on-state voltage drop is reduced by 32.75%. Secondly, the differential specific on-resistance is reduced by 42.33%. Finally, under the same on-state voltage drop, the turn-off energy is reduced more than 50.00%. At the end of the paper, it is explored that what effects the physical parameter of the P+ shielding region in the proposed structure have on the steady state performances.

Applications, Prospects and Challenges of Silicon Carbide Junction Field Effect Transistor (SIC JFET)

Properties of Silicon Carbide Junction Field Effect Transistor (SiC JFET) such as high switching speed, low forward voltage drop and high temperature operation have attracted the interest of power electronic researchers and technologists, who for many years developed devices based on Silicon (Si). A number of power system Engineers have made efforts to develop more robust equipment including circuits or modules with higher power density. However, it was realized that several available power semiconductor devices were approaching theoretical limits offered by Si material with respect to capability to block high voltage, provide low on-state voltage drop and switch at high frequencies. This paper presents an overview of the current applications of SiC JFET in circuits such as inverters, rectifiers and amplifiers. Other areas of application reviewed include; usage of the SiC JFET in pulse signal circuits and boost converters. Efforts directed toward mitigating the observed increase in electromagnetic interference were also discussed. It also presented some areas for further research, such as having more applications of SiC JFET in harsh, high temperature environment. More work is needed with regards to SiC JFET drivers so as to ensure stable and reliable operation, and reduction in the prices of SiC JFETs through mass production by industries.

New Bi-Mode Gate-Commutated Thyristor Design Concept for High-Current Controllability and Low ON-State Voltage Drop

A new design approach for bi-mode gate-commutated thyristors (BGCTs) is proposed for high-current controllability and low ON-state voltage drop. Using a complex multi-cell mixed-mode simulation model which can capture the maximum controllable current (MCC) of large area devices, a failure analysis was performed to demonstrate that the new design concept can increase the MCC by about 27% at room temperature and by about 17% at 400 K while minimizing the ON-state voltage drop. The simulations depict that the improvement comes from the new approach to terminate the GCT part in the BGCT way of intertwining GCT and diode regions for reverse conducting operation.

A novel optimization design for 3.3 kV injection-enhanced gate transistor

This paper introduces a homemade injection-enhanced gate transistor (IEGT) with blocking voltage up to 3.7 kV. An advanced cell structure with dummy trench and a large cell pitch is adopted in the IEGT. The carrier concentration at the N-emitter side is increased by the larger cell pitch of the IEGT and it enhances the P—i—N effect within the device. The result shows that the IEGT has a remarkablely low on-state forward voltage drop (VCE(sat)) compared to traditional trench IGBT structures. However, too large cell pitch decreases the channel density of the trench IEGT and increases the voltage drop across the channel, finally it will increase the VCE(sat) of the IEGT. Therefore, the cell pitch selection is the key parameter consideration in the design of the IEGT. In this paper, a cell pitch selection method and the optimal value of 3.3 kV IEGT are presented by simulations and experimental results.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through (LPT) carrier stored trench bipolar transistor (CSTBT) with buried p-layer (BP) is proposed in this paper. Since the negative charges in the BP layer modulate the bulk electric field distribution, the electric field peaks both at the junction of the p base/n-type carrier stored (N-CS) layer and the corners of the trench gates are reduced, and new electric field peaks appear at the junction of the BP layer/N− drift region. As a result, the overall electric field in the N− drift region is enhanced and the proposed structure improves the breakdown voltage (BV) significantly compared with the LPT CSTBT. Furthermore, the proposed structure breaks the limitation of the doping concentration of the N—CS layer (NN—CS) to the BV, and hence a higher NN—CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop (Vce(sat)) can be obtained with almost constant BV. The results show that with a BP layer doping concentration of NBP = 7 × 1015 cm−3, a thickness of LBP = 2.5 μm, and a width of WBP = 5 μm, the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V, with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3. However, with the same N−-drift region thickness of 150 μm and NN—CS, the BV of the CSTBT decreases from 1598 V to 247 V. Meanwhile, the Vce(sat) of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN—CS increasing from 5 × 1015 cm−3 to 2.5 × 1016 cm−3.

Integrated SiC Anode Switched Thyristor Modules for Smart-Grid Applications

Silicon Carbide Anode Switched Thyristors (ASTs) overcome major limitations of conventional Si and SiC IGBT and GTO Thyristor solutions by providing robust, latch-up free turn-off at high currents, current saturation in the output characteristics, and a wide safe operating area (SOA) through series current controlled device turn-off. In this work, detailed static and switching characteristics of 6.5 kV-class SiC ASTs are reported, which include a low on-state voltage drop of 4 V at 100 A/cm2, slight positive temperature co-efficient of Von, current saturation at &gt; 100 A Cathode currents and fast turn-on and turn-off times of 500 ns while switching 1300 V and 20 A.