Low-density Parity-check Decoder Research Articles

Iterative Interference Cancellation for Multi-Carrier Modulation in MIMO-DWT Downlink Transmission

The Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing (MIMO-OFDM) scheme represents the dominant radio interface for broadband multicarrier communication systems. However, with insufficient Cyclic Prefixes (CP), Inter-Symbol Interference (ISI) and Inter-Carrier Interference (ICI) occur due to the time-varying multipath channel. This means that the performance of the system will be degraded. In this paper, we investigate the interference problem for a MIMO Discrete Wavelet Transform (MIMO-DWT) system under the effect of the downlink LTE channel. A Low-Density Parity-Check (LDPC) decoder is used to estimate the decoded signal. The proposed iterative algorithm uses the estimated decoded signal to compute the components required for ICI/ISI interference reduction. In this paper, Iterative Interference Cancellation (IIC) is employed to mitigate the effects of interference that contaminates the received signal due to multiple antenna transmission and a multipath channel. An equalizer with minimum mean square error is considered. We compare the performance of our proposed algorithm with the traditional MIMO-OFDM scheme in terms of bit error probability under insufficient CP. Simulation results verify that significant improvements are achieved by using IIC and MIMO-IIC for both systems.

Novel memory efficient LDPC decoders for beyond 5G

Beyond-5G wireless networks are expected to gain a excellent trade-off among computational accuracy, latency, and efficient use of available resources. This poses a significant challenge to the channel decoder. In this paper, a novel memory efficient algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity and hardware resources. The algorithm, called Check Node Self-Update (CNSU) algorithm, is based on layered normalized min-sum (LNMS) decoding algorithm while utilizing iteration parallel techniques to integrate both Variable Nodes (VNs) message and A-Posterior Probability(APP) message into the Check Nodes (CNs) message, which eliminates memories of both the VNs message and the APP message as well as updating module of APP message in CNs unit. Based on the proposed CNSU algorithm, design of partially parallel decoder architecture and serial simulations followed by implementation on the Stratix II EP2S180 FPGA are presented. The results show that the proposed algorithm and implementation bring a significant gain in efficient using of available resources, include reducing hardware memory resources and chip area while keeping the benefit of bit-error-rate (BER) performance and speeding up of convergence with LNMS, which are beneficial to apply in Beyond-5G wireless networks.

Transmitting Extra Bits With Cyclically Shifted LDPC Codes

In this letter, we propose a simple yet efficient coding scheme to transmit extra bits by cyclically shifting a low-density parity-check (LDPC) coded sequence without any additional consumption in bandwidth or transmission energy. At the transmitter, the payload data is encoded into an LDPC coded sequence and then cyclically shifted under a pattern specified by the extra bits. At the decoder, the extra bits are first retrieved by estimating the number of cyclic shifts based on the hard or soft syndromes. After removing the effect of cyclic shift, the payload data is recovered by the LDPC decoder. Simulation results show that, with a 5G LDPC code of length 1910, up to 10 extra bits can be reliably transmitted with negligible influence on the reliability of the LDPC coded data.

Efficient Parallel Decoding Architecture for Cluster Erasure Correcting 2-D LDPC Codes for 2-D Data Storage

Native 2-D low-density parity-check (LDPC) codes provide 2-D burst erasure correction capability and have promising applications in two-dimensional magnetic recording (TDMR) technology. Though carefully constructed rastered 1-D LDPC codes can provide 2-D burst erasure correction, they are not as efficient as 2-D native codes constructed for handling the 2-D span of burst erasures. Our contributions are twofold. First, we propose a new 2-D LDPC code with girth greater than 4 by generating a parity-check tensor through stacking permutation tensors of size $p\times p\times p$ along with the $i,j,k$ -axes. The permutations are achieved through circular shifts on an identity tensor along different coordinate axes in such a way that it provides a burst erasure correction capability of at least $p\times p$ . Second, we propose a fast, efficient, and scalable hardware architecture for a parallel 2-D LDPC decoder based on the proposed code construction for data storage applications. Through efficient indexing of the received messages in an RAM, we propose novel routing mechanisms for messages between the check nodes and variable nodes through a set of two barrel shifters, producing shifts along two axes. Through simulations, we show that the performance of the proposed 2-D LDPC codes matches a 1-D QC-LDPC code, with a sharp waterfall drop of three to four orders of magnitude over ~0.3 dB, for random errors over code sizes of ~32 kbits or equivalently ~ $180\times 180 2$ -D arrays. Furthermore, we prove that the proposed native 2-D LDPC codes outperform their 1-D counterparts in terms of 2-D cluster erasure correction ability. For $p=16$ and code arrays of size $48\times 48$ , we implemented the proposed design architecture on a Kintex-7 KC-705 field-programmable gate array (FPGA) kit, achieving a significantly high worst case throughput of 12.52 Gb/s at a clock frequency of 163 MHz.

Trapping Sets of Quantum LDPC Codes

Iterative decoders for finite length quantum low-density parity-check (QLDPC) codes are attractive because their hardware complexity scales only linearly with the number of physical qubits. However, they are impacted by short cycles, detrimental graphical configurations known as trapping sets (TSs) present in a code graph as well as symmetric degeneracy of errors. These factors significantly degrade the decoder decoding probability performance and cause so-called error floor. In this paper, we establish a systematic methodology by which one can identify and classify quantum trapping sets (QTSs) according to their topological structure and decoder used. The conventional definition of a TS from classical error correction is generalized to address the syndrome decoding scenario for QLDPC codes. We show that the knowledge of QTSs can be used to design better QLDPC codes and decoders. Frame error rate improvements of two orders of magnitude in the error floor regime are demonstrated for some practical finite-length QLDPC codes without requiring any post-processing.

Improving LDPC Decoding Performance for 3D TLC NAND Flash by LLR Optimization Scheme for Hard and Soft Decision

Low-density parity-check (LDPC) codes have been widely adopted in NAND flash in recent years to enhance data reliability. There are two types of decoding, hard-decision and soft-decision decoding. However, for the two types, their error correction capability degrades due to inaccurate log-likelihood ratio (LLR) . To improve the LLR accuracy of LDPC decoding, this article proposes LLR optimization schemes, which can be utilized for both hard-decision and soft-decision decoding. First, we build a threshold voltage distribution model for 3D floating gate (FG) triple level cell (TLC) NAND flash. Then, by exploiting the model, we introduce a scheme to quantize LLR during hard-decision and soft-decision decoding. And by amplifying a portion of small LLRs, which is essential in the layer min-sum decoder, more precise LLR can be obtained. For hard-decision decoding, the proposed new modes can significantly improve the decoder’s error correction capability compared with traditional solutions. Soft-decision decoding starts when hard-decision decoding fails. For this part, we study the influence of the reference voltage arrangement of LLR calculation and apply the quantization scheme. The simulation shows that the proposed approach can reduce frame error rate (FER) for several orders of magnitude.

LDPC Decoder Design Using Compensation Scheme of Group Comparison for 5G Communication Systems

This paper presents a dual-mode low-density parity-check (LDPC) decoding architecture that has excellent error-correcting capability and a high parallelism design for fifth-generation (5G) new-radio (NR) applications. We adopted a high parallelism design using a layered decoding schedule to meet the high throughput requirement of 5G NR systems. Although the increase in parallelism can efficiently enhance the throughput, the hardware implementation required to support high parallelism is a significant hardware burden. To efficiently reduce the hardware burden, we used a grouping search rather than a sorter, which was used in the minimum finder with decoding performance loss. Additionally, we proposed a compensation scheme to improve the decoding performance loss by revising the probabilistic second minimum of a grouping search. The post-layout implementation of the proposed dual-mode LDPC decoder is based on the Taiwan Semiconductor Manufacturing Company (TSMC) 40 nm complementary metal-oxide-semiconductor (CMOS) technology, using a compensation scheme of grouping comparison for 5G communication systems with a working frequency of 294.1 MHz. The decoding throughput achieved was at least 10.86 Gb/s without evaluating early termination, and the decoding power consumption was 313.3 mW.

High performance binary LDPC-coded OFDM systems over indoor PLC channels

Power line communication (PLC) technology is actually among the most renowned technologies for home environments due to their low-cost installation opportunities. In this study, the bit error rate (BER) performances of binary low-density parity check (LDPC) coded orthogonal frequency-division multiplexing (OFDM) systems have been considered over indoor PLC channels. Performances comparison of diverse soft and hard decision LDPC decoder schemes such as Min-Sum (MS), weighted bit flipping (WBF), gradient descent bit-flip (GDBF), noisy gradient descent bit-flip (NGDBF) and its few variants including the single-bit NGDBF (S-NGDBF), multi-bit NGDBF (M-NGDBF) and smoothed-multi-bit NGDBF (SM-NGDBF) decoders were examined in the modeled network. To evaluate the BER performance analyses three different PLC channel scenarios were generated by using new and more realistic PLC channel model proposal were also employed. All of the simulations performed in Canete’s PLC channel model showed that remarkable performance improvement can be achieved by using short-length LDPC codes. Especially, the improvements are striking when the MS or SM-NGDBF decoding algorithms are employed on the receiver side.

Physical Layer Latency Management Mechanisms: A Study for Millimeter-Wave Wi-Fi

Emerging applications in fields such as extended reality require both a high throughput and low latency. The millimeter-wave (mmWave) spectrum is considered because of the potential in the large available bandwidth. The present work studies mmWave Wi-Fi physical layer latency management mechanisms, a key factor in providing low-latency communications for time-critical applications. We calculate physical layer latency in an ideal scenario and simulate it using a tailor-made simulation framework, based on the IEEE 802.11ad standard. Assessing data reception quality over a noisy channel yielded latency’s dependency on transmission parameters, channel noise, and digital baseband tuning. Latency in function of the modulation and coding scheme was found to span 0.28–2.71 ms in the ideal scenario, whereas simulation results also revealed its tight bond with the demapping algorithm and the number of low-density parity-check decoder iterations. The findings yielded tuning parameter combinations for reaching Pareto optimality either by constraining the bit error rate and optimizing latency or the other way around. Our assessment shows that trade-offs can and have to be made to provide sufficiently reliable low-latency communication. In good channel conditions, one may benefit from both the very high throughput and low latency; yet, in more adverse situations, lower modulation orders and additional coding overhead are a necessity.

Self-Corrected Belief-Propagation Decoder for Source Coding With Unknown Source Statistics

This letter describes a practical Slepian-Wolf source coding scheme based on Low Density Parity Check (LDPC) codes. It considers the realistic setup where the parameters of the statistical model between the source and the side information are unknown. A novel Self-Corrected Belief-Propagation (SC-BP) algorithm is proposed in order to make the coding scheme robust to incorrect model parameters by introducing some memory inside the LDPC decoder. A Two Dimensional Density Evolution (2D-DE) analysis is then developed to predict the theoretical performance of the SC-BP decoder. Both the 2D-DE analysis and Monte-Carlo simulations confirm the robustness of the SC-BP decoder. The proposed solution allows for an important complexity reduction and shows a performance very close to existing methods which jointly estimate the model parameters and the source sequence.

Belief Propagation Decoding of Short Graph-Based Channel Codes via Reinforcement Learning

In this work, we consider the decoding of short sparse graph-based channel codes via reinforcement learning (RL). Specifically, we focus on low-density parity-check (LDPC) codes, which for example have been standardized in the context of 5G cellular communication systems due to their excellent error correcting performance. LDPC codes are typically decoded via belief propagation on the corresponding bipartite (Tanner) graph of the code via flooding, i.e., all check and variable nodes in the Tanner graph are updated at once. We model the node-wise sequential LDPC scheduling scheme as a Markov decision process (MDP), and obtain optimized check node (CN) scheduling policies via RL to improve sequential decoding performance as compared to flooding. In each RL step, an agent decides which CN to schedule next by observing a reward associated with each choice. Repeated scheduling enables the agent to discover the optimized CN scheduling policy which is later incorporated in our RL-based sequential LDPC decoder. In order to reduce RL complexity, we propose a novel graph-induced CN clustering approach to partition the state space of the MDP in such a way that dependencies between clusters are minimized. Compared to standard decoding approaches from the literature, some of our proposed RL schemes not only improve the decoding performance, but also reduce the decoding complexity dramatically once the scheduling policy is learned. By concatenating an outer Hamming code with an inner LDPC code which is decoded based on our learned policy, we demonstrate significant improvements in the decoding performance compared to other LDPC decoding policies.

Reduce the Resources Utilization of LDPC Decoder Based on Min-Sum Decoder for Spread Spectrum Applications

Communications with spread spectrum (SS) have attracted attention because of their channel attenuation immunity and low potential for interception. Aside from some extra features such as basic transceiver structures, the analogy alternative to digital SS systems would be chaotic communication. In this brief, Differential Chaos Shift Keying (DCSK) systems, non-periodic and random characteristics among chaos carriers and their interaction with soft data are designed based on low-density parity-check ( LDPC) codes. Because of simple structure and magnificent error correction capability. Using the development kit Xilinx kintex7 FPGA, we investigate the DCSK communication system’s hardware efficiency and resource requirement tendencies based on the LDPC decoding algorithm Min-Sum over AWGN channel. The results demonstrate that the proposed system model has major improvements in Bit Error Rate ( BER) performance and the real-time process. The Min-Sum decoder has comparatively fewer FPGA resources than other decoders for soft decisions. The implemented system achieves a coding gain of 10-4 BER efficiency with 5.6 dB associate Eb/No.

A Reconfigurable and Pipelined Architecture for Standard-Compatible LDPC and Polar Decoding

With low-density parity-check (LDPC) codes and polar codes selected as the standard codes for the fifth generation (5G) enhanced Mobile Broad Band scenario (eMBB), a decoding architecture that can simultaneously support the decoding of control and data plane becomes necessary at the terminal side to meet the raising requirement for 5 G network deployment. Due to the special structure of LDPC codes according to the Release 15 (R15) 5G standard, a straight-forward extension of the existing reconfigurable scheme is in general difficult. Therefore in this paper, a unified decoding architecture is proposed that can be reconfigured to either LDPC codes or polar codes. Due to various differences between the two codes such as parity-check matrices, codeword lengths and iterative methods, a joint decoding algorithm is introduced by reordering basic decoding operations to the unified add-comparison-add pattern for both codes. Then, a pipelined structure of reconfigurable decoding unit (RDU) is presented correspondingly which is fully compatible with all decoding patterns of the R15 standard. And finally, a reconfigurable decoder is proposed with multiple levels of parallelism, and the reconfiguration scheme is introduced to improve the hardware utilization and decoding efficiency. The proposed decoder is implemented in FPGA and ASIC, respectively, and has achieved state-of-the-art performance in throughput and area efficiency compared to LDPC-only and polar-only decoders.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

Reliability Ratio-Based Serial Algorithm of LDPC Decoder for Turbo Equalization Schemes

Serial decoding algorithms of low-density parity-check (LDPC) code converge efficiently with low errors. Previously, a serial decoding algorithm, named a shuffled belief-propagation (SBP), was applied in turbo equalization of bit-patterned magnetic recording (BPMR) systems. With the SBP algorithm, an LDPC decoder converged twice as fast as one using conventional BP algorithms. We further improved the convergence speed of SBP by updating the messages in an adaptive order, which played a flexible role throughout decoding. We proposed two adaptive-serial algorithms for LDPC codes in turbo equalization. One updated the messages using the extrinsic loglikelihood ratio (LLR) and the result of the parity-check equation checking. The second contained an additional rule that tracked the LLR sign changes in each iteration. Both algorithms converged faster and with lower bit error rates (BERs) than the SBP and previous adaptive-serial algorithms in a BPMR system with media noise.

A novel error correction protocol for continuous variable quantum key distribution

Reconciliation is a key element of continuous-variable quantum key distribution (CV-QKD) protocols, affecting both the complexity and performance of the entire system. During the reconciliation protocol, error correction is typically performed using low-density parity-check (LDPC) codes with a single decoding attempt. In this paper, we propose a modification to a conventional reconciliation protocol used in four-state protocol CV-QKD systems called the multiple decoding attempts (MDA) protocol. MDA uses multiple decoding attempts with LDPC codes, each attempt having fewer decoding iteration than the conventional protocol. Between each decoding attempt we propose to reveal information bits, which effectively lowers the code rate. MDA is shown to outperform the conventional protocol in regards to the secret key rate (SKR). A 10% decrease in frame error rate and an 8.5% increase in SKR are reported in this paper. A simple early termination for the LDPC decoder is also proposed and implemented. With early termination, MDA has decoding complexity similar to the conventional protocol while having an improved SKR.

Generalized weighted bit-flipping LDPC decoding for asymmetric optical channels

Efficient low-complexity and low-latency forward error correction (FEC) decoding is vital in high-speed optical receivers. The weighted bit-flipping (WBF) decoding algorithm is a low-complexity and high-performance iterative decoder for low-density parity-check (LDPC) codes, devised for symmetric Gaussian channels. In this paper, we present a generalization of the WBF algorithm and its variants to discrete and continuous asymmetric optical channels which have signal-dependent noises. We have employed a fully analytical approach to derive the generalized WBF decoders, and show that they can achieve a net coding gain within 0.5 dB of that of the soft-decision near-optimal decoding.

An optimized initialization for LDPC decoding over GF(q) in impulsive noise environments.

Modern navigation satellite communication has the characteristic of high transmitting rate. To avoid bit errors in data transmission, low density parity check (LDPC) codes are widely recognized as efficient ways for navigation communication. Conventionally, the LDPC decoding is applied for additive white Gaussian noise (AWGN) channel and degrades severely while facing the impulsive noise. However, navigation communication often suffers from impulsive interference due to the occurrence of high amplitude "spikes". At this time, the conventional Gaussian noise assumption is inadequate. The impulsive component of interference has been found to be significant which influences the reliability of transmitted information. Therefore the LDPC decoding algorithms for AWGN channel are not suitable for impulsive noise environments. Consider that LDPC codes over GF(q) perform better than binary LDPC in resisting burst errors for current navigation system, it is necessary to conduct research on LDPC codes over GF(q). In this paper, an optimized initialization by calculating posterior probabilities of received symbols is proposed for non-binary LDPC decoding on additive white Class A noise (AWAN) channel. To verify the performance of the proposed initialization, extensive experiments are performed in terms of convergence, validity, and robustness. Preliminary results demonstrate that the decoding algorithm with the optimized initialization for non-binary LDPC codes performs better than the competing methods and that of binary LDPC codes on AWAN channel.

Performance enhancement of optical camera communication system using optical camera communication coding and region‐of‐interest detection

Optical camera communication (OCC) is considered an important transmission scheme in implementing indoor navigation, beacons, and other Internet of Things applications. One of the disadvantages of OCC, however, is that transmission is successful only if the line-of-sight requirement is satisfied between transmitting LED lamps and receiving image sensors. Any obstacle between them or movement of the receiver direction causes a reduction in the light signal and leads to a burst error, and its compensation is not easy. A low-density parity check (LDPC) code is employed in the OCC to overcome burst error. To improve the performance further, a region of interest area detection is proposed that utilizes only the centre part of an image frame for LDPC decoding rather than using the whole area measurement. The LDPC codes are tested using an appropriate OCC packet structure, and its performance is compared with that of polar codes. The experimental results indicate that LDPC coding is more suitable in OCC systems. It is found that the proposed LDPC coding scheme not only recovers the data from burst errors but also enhances the transmission distance. In particular, soft-decision LDPC decoding shows more resistance to burst errors and bit loss.

Comparison of single-lane 100 Gb/s PAM-4 and DB-PAM-4 signals transmission based on 12G receiver with FFE and LDPC

Using low-bandwidth receivers to transmit single-wavelength 100 Gb/s data provides a low-cost and high-rate solution for the next generation passive optical networks (PONs). In this paper, we experimentally investigate the transmission of single-wavelength 100 Gb/s four-level pulse–amplitude modulation (PAM-4) and duobinary PAM-4 (DB-PAM-4) signal with a cost-effective 12 GHz PIN receiver. Feed-forward equalization (FFE) in conjunction with low-density parity-check (LDPC) is applied to enhance the bit error rate (BER) performance of the 25-km standard single-mode fiber (SSMF) transmitted signal. The Max-Log-maximum a posteriori (MAP) algorithm is utilized to computing soft information and provide it to LDPC decoding. As a result, under the same limited-bandwidth transmission conditions, DB-PAM-4 shows superior performance compared to PAM-4, reducing BER below the LDPC threshold 10−2. Error-free 25 km-transmission of 100 Gb/s DB-PAM-4 signal is realized employing 35-tap FFE and LDPC. On the contrast, the BER of PAM-4 cannot even be lower than 10−1, even with more taps and longer training sequences.