Low-voltage Differential Signaling Research Articles

A compact and highly integrated 128-channel FPGA-based readout electronics for nuclear imaging application

As silicon photomultiplier (SiPM) technology develops, its possible applications are being growingly expanded. However, the current technical obstacle is the signal readout from large-scale, multi-pixel SiPMs, especially in a large nuclear imaging device. Although the application-specific integrated circuits (ASICs) provide ways to reach that goal, it needs a long period with iterative electronic process and a very high cost. We developed a high-integrated positron emission tomography (PET) electronics system with field programmable gate array based charge-to-digital converter (FPGA-QDC) technology instead of the ASICs. Unlike traditional FPGA-based charge readout method in which low-voltage differential signaling (LVDS) receivers serve as analog voltage comparators, in the proposed electronics system voltage-referenced receivers work as analog comparators.Theoretically, nearly all of input/output (I/O) ports in the FPGA can achieve the function of analog comparators using voltage-referenced I/O standard. The electronics system is constructed using off-the-shelf low-cost commercial components. Therefore, it is feasible to fast build a distributed readout system with multiple such electronics system. The flexibility and reconfigurability of the FPGA provide multi-channel grouping and diverse triggering for different kinds of detector configurations, such as row/column summation and resistor-based readout. These features are greatly sought after in readout electronics for the SiPM-based radiation detectors. Experimental results show that the proposed highly-integrated electronics system overcomes the bottleneck that has limited the development of advanced PET detectors and scanners.

Constant Fraction Discriminator for NA62 experiment at CERN

A new Constant Fraction Discriminator with additionalTime over Threshold measurement capabilities will be presented.It operates in a wide dynamic range of 1:150, with an excellent timeresolution of better than 70 psover one order of magnitude of the input signals.It is highly customizable for different signal shapes and thresholds,using remotely-programmableparameters for Detector Control System commands.Two outputs, each in the Nuclear Instrumentation Module and Low VoltageDifferentialSignaling standards,provide a precise signal arrival time and Time over Thresholdinformation with programmable thresholds.The technical specification and performance measured with cosmic rays and in thehigh-intensity NA62 experiment will be reported.

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS).A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

Using FPGA-Based AMC Carrier Boards for FMC to Implement Intelligent Data Acquisition Applications in MTCA Systems Using OpenCL

The Micro Telecommunications Computing Architecture (MTCA) standard is widely used in developing advanced data acquisition and processing solutions in the big physics community. The number of applications implemented using commercial Advanced Mezzanine Cards (AMC) using AMD-Xilinx and Intel® Field Programmable Gate Array (FPGA) systems on chips is growing due to the flexibility and scalability of these reconfigurable hardware devices and their suitability to implement intelligent applications using artificial intelligence and machine learning techniques. The paper presents the specific design methodologies for hardware acceleration proposed by both FPGA manufacturers. Comparative results are obtained from two different software/hardware setups using two different AMCs, one based on Intel® FPGA Arria 10 and another based on Xilinx ZynqMP. The paper illustrates the process of how to modify the board support package, required by the hardware acceleration methodology, to implement the JESD204B and Low-Voltage Differential Signaling (LVDS) interfaces with the FPGA Mezzanine Card (FMC) modules containing the ADCs, to prepare the AMC cards to implement such kind of applications. The data acquisition and processing implementation inside these reference designs, with both languages OpenCL and High-Level Synthesis (HLS), is described. An important feature, needed for many applications in the big physics field, is the interface with the Experimental Physics and Industrial Control System (EPICS) software framework using the ITER Nominal Device Support framework, which is briefly described.

NTIMP1—A Fast Pulse Readout Chip With 1.2 V Power Supply Applied to the Diamond Detector in HIAF

A very fast pulse readout ASIC, NTIMP1, with 1.2 V power supply is presented in this work. It is going to be used as front-end electronics (FEE) for reading out the diamond detector signals in the TOF (Time of Flight) wall of RIBLL2 experiment of the High Intensity Heavy Ion Accelerator Facility (HIAF), China. So that an 8-channel fast front-edge readout chip named as NTIMP1 is proposed in this work. Each channel of NTIMP1 has a high-bandwidth preamplifier (with adjustable thresholds) dealing with differential current input, a fast hysteresis discriminator, and a LVDS (Low-Voltage Differential Signaling) module ensuring long-distance signal transmission. Fabricated with 0.13 μm standard CMOS Technology, NTIMP1 can get an input ranging from 2 fC to 2000 fC and the input impedance of the preamplifier can be adjusted externally with an off-chip resistor, so as to match with the electrode impedance of diamond detector. The bandwidth of the preamplifier is 495.5 MHz, which allows a very short signal peaking time of no more than 1 ns. The jitter of the leading edge is lower than 15 ps with 100 fC input charge suggesting that NTIMP1 is suitable for high-resolution TOF measurement as well as time-slewing correction.

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An FPGA Charge-to-Digital Converter Based on Voltage-Referenced Receivers for PET Applications

A field programmable gate array (FPGA) voltage-referenced standard receiver based charge-to-digital converter (QDC) was proposed. The QDC is based on a linear discharge scheme. In the linear discharge circuit, typically, a low-voltage differential signaling (LVDS) receiver serves as a voltage comparator. Our proposed scheme takes advantage of voltage-referenced standard in the FPGA instead of the LVDS standard, which maximizes the capability of multichannel and multifunctionality. The linearity differences were compared between the voltage-referenced receivers and the LVDS receiver. To validate the scheme for radiation detector application, a 32-channel electronics prototype based on the proposed structure was developed. A positron emission tomography (PET) detector module was built. The detector is made up of a 15 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 15 LYSO array directly coupled with two silicon photomultipliers (SiPM) at two ends. The mean energy resolution for single crystal at the center can reach 17.9%. The linear discharge scheme based on voltage-referenced receivers provides a promising method for a compact, multichannel electronics readout system for radiation detector application.

A High Time-Resolved Front-End ASIC for APD Array Detector in Nuclear Resonant Scattering Experiments With Synchrotron Radiation

A high time-resolved front-end readout chip has been developed for avalanche-photodiode (APD) array detectors in nuclear resonant scattering (NRS) experiments. The chip has eight channels. Each channel consists of a preamplifier, a voltage discriminator, an open-drain output driver, and a local digital-to-analog converter (LDAC). The application-specific integrated circuit (ASIC) chip has been designed and fabricated in a 0.13- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology with a chip size of 1.1 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times2.3$ </tex-math></inline-formula> mm. The electrical characterizations of all eight channels demonstrate good time resolution (TR) (rms) on the output pulse leading edge, with the measurement result better than 25 ps for high input signal charges (>30 fC) and better than 98 ps for low input signal charges (8–30 fC), for an APD sensor capacitance as large as 15 pF. The equivalent noise charge (ENC) received from the measurement can be represented as ENC = 592.4 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> + 50.7 e <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−</sup> /pF. The power consumption is 17.6 mW per channel: 2.7 mW for the preamplifier–discriminator stage and 14.9 mW for the output low-voltage differential signaling (LVDS) driver.

A 13 Gbps 1:16 deserializer ASIC for NICA multi purpose detector project

This paper presents the design and test results of a 13 Gbps 1:16 deserializer ASIC fabricated in a 55 nm CMOS technology for Nuclotron-based Ion Collider fAcility (NICA) Multi Purpose Detector (MPD) project. The deserializer would be used in the downlink data transmission of MPD readout system to recover the serial data from the back-end to the parallel data for the front-end. The ASIC adopts a tree-type structure, consisting of a high-speed data receiver (RXDATA), a high-speed clock receiver (RXCLK), four levels of demultiplexer (DEMUX) modules, clock dividers and 16 Low-Voltage Differential Signaling (LVDS) drivers. The demultiplexer modules are composed of different numbers of high-speed DEMUX unit and low-speed DEMUX unit. The high-speed DEMUX unit and the high-frequency clock divider adopt an optimized compressed current mode logic (CML) differential structure to ensure the bandwidth with limited voltage headroom. The low-speed DEMUX unit and the low-frequency clock divider use CMOS latch to save power consumption. The duty cycle correction (DCC) circuit and the clock aligner are employed in the clock paths to ensure the correct duty cycle and aligned clock edges. In the chip test, the ASIC receives 13 Gbps serial data and outputs 16 channels of 812.5 Mbps data correctly with wide-open eye diagram. The tested power consumption is 203 mA with 1.2 V power supply including the RXDATA, the RXCLK and the 16 channels of LVDS drivers, and the core power consumption is 122.7 mA.

In-Place Evaluation of Powering and Signaling Within Fan-Out Multiple IC Chip Packaging

This article confirms the advantage of fan-out (FO) packaging in the electrical performance of power delivery among integrated circuit (IC) chips with the best use of land side capacitors (LSCs). On-chip in-place waveform measurements quantitatively evaluate the integrity of powering and signaling within FO wafer level packaging (FOWLP) multiple chip module (MCM) demonstrators, where a pair of IC chips are assembled with LSCs with different sizes and structures. The IC chip incorporates an array of 12 digital cores and on-chip waveform monitor (OCM) circuits. Each digital core consists of a low-voltage differential signaling (LVDS) transceiver channel that is backed by a static random access memory (SRAM)-based built-in self test (BIST) module and supplied by an on-chip voltage regulator module (VRM). The LSCs are placed on the bottom side of an FO interposer and inserted between the output of VRM and the ground plane almost ideally with the shortest length of physical traces. A Si membrane capacitor of 10 nF sustains the lowest power line impedance over the frequency range of 2.0 GHz more constantly than a multilayer ceramic counterpart, and attenuates the high-order harmonic frequency components to the clocking frequency at 750 MHz. The leverage of LSCs in powering also improves signaling and helps achieve the wider eye openings in LVDS channels. The implications are elaborated for the capacitor selections with respect to the physical types of capacitors, the size of capacitances, and the level of shares in power delivery among digital cores, all toward the higher level of integrity in powering and signaling in FOWLP MCMs.

A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution

This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. A reference sharing scheme with reduced buffers is proposed to improve area-and-power efficiency, which is essential for multi-channel systems. Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. The prototype ADC is designed in a 0.18-μm process with peripheral circuits integrated, including low-voltage differential signaling (LVDS), bandgap, etc. It achieves a robust and calibration-free performance with 68.25-dB signal to noise and distortion ratio (SNDR) and 82.19-dB spurious-free dynamic range (SFDR), translating into a competitive figure of merit (FoM) of 0.47 pJ/conversion-step among other high-resolution ADCs used in ultrasound applications.

Development of a front-end electronics for thin-gap resistive plate chamber

To cope with the challenge of high hit rates in some applications, the new-generation large-area Resistive Plate Chamber (RPC) with 1 mm thin gap was proposed. Compared to the RPC generation presently, the signal of the thin-gap RPC is much weaker (of the order of hundreds of μV) and faster (pulse width of about 5 ns). Hence a new-generation Front-End (FE) electronics needs to be developed for the thin-gap RPC. The FE board contains 8 independent electronic channels, each with an amplifier, a discriminator, and a Low-Voltage Differential Signaling (LVDS) transmitter. The amplifier is made of discrete components, with particular emphasis on SiGe:C transistors. A simplified but stable power system is designed for the FE board, and its status can be monitored in real-time. The test results show that the overall charge gain of the FE amplifier reaches 0.4 mV/fC, with very low noise (lower than 700 μV RMS with up to 10 pF input detector capacitance), and good linearity when the amplitude of the input amplitude is lower than 3 mV. The -3-dB bandwidth of the amplifier reaches 154 MHz. The jitter caused by the electronics (including amplifier, discriminator and LVDS transmitter) is around 10 ps when the threshold voltage is higher than 20 mV. The maximum event rate per channel exceeds 20 MHz. The cosmic ray test was conducted with two FE boards mounted on a 1 mm thin-gap RPC of 1.4 × 0.4 m2 area. The efficiency of the detector system reaches 95% when the threshold voltage is 20 mV, with almost no accidental coincidence event. The overall time resolution of the detector system is 484 ps. The performance of our FE electronics satisfies the requirement of the thin-gap RPC.

A High Speed Redundant IO Bus for Energy Power Controller System

This paper designs and implements a High Speed Redundant IO Bus for Energy Power Controller System. The physical layer adopts multi-point low-voltage differential signal standard. This bus has the characteristics of high real-time, high throughput and easy expansion. The controller communicates with IO module by A/B bus alternately, monitors link status in real time and collects IO module data. Non real time slots can be used to control non real time messages for IO modules such as time synchronizing and memory monitoring. The controller ARM core runs QNX real-time operating system, and transmits the message needed to communicate with IO modules to the FPGA through DMA. After receiving the message, the FPGA parses the message and automatically fills in the CRC check code and frame end flag at the end of the message. When the FPGA receives the data feedback from the IO module, it performs CRC verification. If the verification passes, it fills the corresponding module receiving buffer. Otherwise, it fills the CRC verification error flag in the register of the corresponding IO module to reduce the load of the arm core.

Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications.

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response

In this work, a generalized power supply induced jitter (PSIJ) model is proposed. The PSIJ sensitivity is obtained based on the evaluation of driver power supply rejection ratio (PSRR) response. The voltage ripple at the driver output is transformed into driver output jitter with the slope of the switching edge. The time-averaged effect of power noise during the time range of driver propagation delay is also considered. The proposed model is applied to estimate the PSIJ sensitivity for typical inverter type of drivers and a low-voltage differential signaling (LVDS) type of current mode differential transmitter. Depending on the transistor working region in the driver, the PSIJ sensitivity frequency dependence could be dominated by either the propagation delay or the PSRR response. The accuracy of the predicted PSIJ sensitivity is verified by simulation. Reasonably good accuracy has been achieved in terms of both the magnitude and phase.

Prototype of simultaneous bidirectional data-transmitter in 65 nm CMOS

This article presents a design and implementation of an I/O circuit block capable of simultaneous bidirectional data-transmission in CMOS integrated circuits. Merging data-transmitter and receiver into common bonding pad is feasible not only to reduce the number of transmission lines from a considerable number of chips, but also to realize more area-efficient data handling in consequence of flexible inter-chip communication. This feature is attractive from the viewpoint of detector systems in high energy experiments, in which reducing materials such as cables from silicon trackers in inner vertex layers is of major importance to suppress multiple-scattering and to achieve good overall detector performances. The circuit block presented here is designed on the basis of a current subtraction circuit and two distinct current-mode logic drivers. Its principle is also applicable to widely-used low-voltage differential signal drivers and easy for process migration. The prototype chip was fabricated in a 65 nm CMOS technology. Working principle has been demonstrated in preliminary laboratory testing.

Design of Time-to-Digital Converters for Time-Over-Threshold Measurement in Picosecond Timing Detectors

In picosecond timing detectors, the time over threshold (TOT) of detector signals is normally required to be measured to enhance the front-edge timing precision. The extremely narrow pulsewidth of these detector signals has posed challenges to the design of time-to-digital converters (TDCs) based on field programmable gate arrays (FPGAs) for TOT measurement. In this article, an FPGA-based tapped-delay-line (TDL)-type TDC is proposed to simultaneously measure the arrival time and TOT time of nuclear pulses. By propagating the hit signal along a single TDL, the proposed bubble-proof encoding scheme can extract the time information of two transitions of hit signal in one measurement. The minimum measurable TOT time is proved to be limited only by the electrical characteristics of low-voltage differential signaling (LVDS) receivers of FPGAs. Through the performance evaluation on the prototype with a Virtex Ultrascale + FPGA, where the minimum measurable TOT time can be as low as 370 ps, the rms precision reaches 3.0 ps for TOT time measurement. Given the pulsewidths ranging from 0.4 to 1.5 ns, the measured TOT time is highly consistent with the direct readout values from the oscilloscope in a wide temperature range. To apply the TDC into a microchannel plate photomultiplier tube (MCP-PMT)-based timing detector, the front-end electronics board with a dual-threshold TOT measurement is constructed. The joint beam test results show that the coincidence time resolution of two identical detector channels can be improved from 36.5 to 10.3 ps, which demonstrates the significance of TOT measurement to modern picosecond timing detectors.

Towards the Prediction of SpaceWire Radiated Emissions Employing an LVDS Signal Emulator

The majority of the past and current ESA’s, NASA’s, and JAXA’s science missions utilize broadly SpaceWire (SpW) Links, with Low Voltage Differential Signaling (LVDS) for the physical layer, to transfer mission data. Electromagnetic Compatibility (EMC) and Electromagnetic Interference (EMI) problems caused by harnesses’ radiated emissions remain a constant open issue in every mission due to the scientific payload sensitivity. A common cause of radiated emissions from shielded cable bundles can be traced to the currents flowing on the shield of the harness. This work aims to present a complete methodology for predicting the Electric field emissions in the case of an operating SpW link, while it can be expanded to any shielded cable which utilizes LVDS. The physical and protocol layer of the link are implemented via a developed LVDS Signal emulator, handling both the characteristics of the signals at the outputs of the LVDS line drivers and the effects of their transmission across the link along with the termination scheme, in order to calculate the common mode current flowing on the shield. The radiated emissions can then be estimated considering the ground material and a detailed harness topology, employing traveling wave antenna theory. The validity of this approach is assessed by comparing the predictions with actual link radiated emissions measurements. Simulation results are in good agreement with the measurements, rendering this methodology a fast tactic for the pre-compliance procedure for the early design stage of the science space mission.

Differential Signaling Compromises Video Information Security Through AM and FM Leakage Emissions

Video display units (VDUs) using differential signaling technology significantly increase the risk of compromising video information security through leakage emissions. This article shows that differential signaling cables act as substantial video leakage sources. A concept is proposed that explains the video leakage principles of VDUs using differential signal cables such as the high-definition multimedia interface (HDMI) cable, digital visual interface (DVI) cable, and the low-voltage differential signaling (LVDS) cable. The emanations of the LVDS cable are closely examined by measuring simultaneously the differential video signal on the LVDS lines and its near- and far-field leakage emissions. From these measurements, several conclusions are drawn that give new insights into the video eavesdropping risk of VDUs using differential signaling methods. Furthermore, a novel video image reconstruction method is proposed that exploits the compromising emanations of a VDU by using frequency demodulation techniques. This article shows that leaked video emanations of VDUs using differential signaling cables are not only amplitude modulated (AM) but also frequency modulated (FM). This strongly implies that the possible algorithmic toolset of malicious video eavesdroppers is much larger than currently assumed. This article investigates several VDU setups at a distance of 10 m, including an ultrahigh-definition video display, three different HDMI cables and two notebooks. Additionally, the AM-based and FM-based video image reconstruction results are discussed and compared.

Design of High Speed and Precision and Low-Power LVDS Driver for CMOS Image Sensor

Aiming at the requirement of high speed and precision, low-power and large-capacity load of serial data interface for aerospace super large array(15k×15k) CMOS image sensor, a design scheme low voltage differential signal (LVDS) driver by combining the split-length method with the pre-emphasis technique is proposed. Firstly, comparing with the general design schemes, the present scheme uses the split-length compensation method to increase effectively the unity-gain bandwidth while keeping the op-amp gain constant. Secondly, the pre-emphasis technique is used to compensate the LVDS driver for high-frequency components to improve the driving capability of the capacitive load and high speed signal integrity (SI). The simulation results show that the accuracy of the common-mode feedback voltage is improved by using the split-length compensation method, and also the common-mode voltage changes below 15 mV. The pre-emphasis technique is used to enhance the amplitude of the high-frequency components lost during the high-speed transmission. The quality of the signal eye diagram during high-speed transmission reduces the bit error rate, and both the transmission rate and the driving load capacity are two times more than the general design (1.2 Gb/s@12 pF), and the quiescent current consumption is only 4.6 mA@12 pF. The present LVDS driver design is implemented in a typical CMOS process of 0.18 μm.