Abstract
In this work, a generalized power supply induced jitter (PSIJ) model is proposed. The PSIJ sensitivity is obtained based on the evaluation of driver power supply rejection ratio (PSRR) response. The voltage ripple at the driver output is transformed into driver output jitter with the slope of the switching edge. The time-averaged effect of power noise during the time range of driver propagation delay is also considered. The proposed model is applied to estimate the PSIJ sensitivity for typical inverter type of drivers and a low-voltage differential signaling (LVDS) type of current mode differential transmitter. Depending on the transistor working region in the driver, the PSIJ sensitivity frequency dependence could be dominated by either the propagation delay or the PSRR response. The accuracy of the predicted PSIJ sensitivity is verified by simulation. Reasonably good accuracy has been achieved in terms of both the magnitude and phase.
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