Low VDS Research Articles

Bulk transport and contact limitation of MoS2 multilayer flake transistors untangled via temperature-dependent transport measurements

Rational use of novel high-performance semiconductors in field-effect transistors (FETs) requires exact knowledge of the dominating charge transport mechanisms. In particular, the distinction between contact- and semiconductor-limited transport is important in FETs with small channel lengths. Here, we analyze the relative contributions of contact limitation and intrinsic conductivity of FETs based on mechanically exfoliated multilayers of the high performance n-type semiconductor molybdenum disulfide (MoS2). Based on a lithography-free fabrication process, we realize FETs with room temperature mobility (μ) of up to 46.8 cm2/Vs and ION/IOFF ratio of up to 105. Using temperature- and bias-dependent charge transport measurements, we are able to show that the intrinsic bulk transport in the flake can be best described by a phonon-limited band transport model with a conductive bulk at room temperature that freezes out upon cooling of the sample. In addition, we notice an increase of μ by a factor of 2–5 when using a self-assembled monolayer (SAM)-modified SiO2/MoS2 interface. More importantly, we show that the choice of drain–source bias (VDS) is crucial when interpreting MoS2 transport measurements, while for large VDS the intrinsic semiconductor transport properties can be observed, a strong contact limitation appears at low VDS. Our combined measurements allow us to distinguish between the effect of bulk and semiconductor/dielectric interface transport and the effect of contact resistance on the electrical transport properties.

Self‐Aligned Megahertz Organic Transistors Solution‐Processed on Plastic

The processing of complex nanoscale electronic structures on plastic substrates is a significant challenge, requiring the combination of low temperature, nonaggressive, and high resolution methods. Here a scalable process flow on plastic is presented tbat enables the fabrication of flexible nano­imprinted organic field‐effect transistors (OFETs) with self‐aligned contacts and solution‐processed semiconductor and dielectric layers, at processing temperatures ≤ 150 °C. OFETs are fabricated with device cutoff frequencies f > 1 MHz at low operating bias V DS = −15 V. The technique allows the patterning of metal structures over four orders of magnitude from 375 nm to 1 mm without the need for a rigid carrier, and provides a fabrication pathway to high performance nanostructured organic circuitry.

Evaluation of the drain—source voltage effect on AlGaAs/InGaAs PHEMTs thermal resistance by the structure function method

The effect of drain—source voltage on AlGaAs/InGaAs PHEMTs thermal resistance is studied by experimental measuring and simulation. The result shows that AlGaAs/InGaAs PHEMTs thermal resistance presents a downward trend under the same power dissipation when the drain—source voltage (VDS) is decreased. Moreover, the relatively low VDS and large drain—source current (IDS) result in a lower thermal resistance. The chip-level and package-level thermal resistance have been extracted by the structure function method. The simulation result indicated that the high electric field occurs at the gate contact where the temperature rise occurs. A relatively low VDS leads to a relatively low electric field, which leads to the decline of the thermal resistance.

Contact Effects in Organic Thin Film Transistors with Different Device Structures

The electrical characteristics of organic thin film transistors (OTFTs) are frequently affected by contact effects, which can seriously reduce the transistor performance. The “parasitic” voltage drop at the contacts, induced by contact resistance, decreases the effective drain-source and gate-source voltages applied to the intrinsic channel of the transistor, reducing the device current. The importance of the contact resistance, Rc, is more relevant in the case of high carrier mobility and/or small channel length devices, where its value may become comparable or even larger than the channel resistance. Rc appears to be strongly affected by the device architecture and much higher Rc-values are typically observed, at low drain voltages, in coplanar structures (i.e. Bottom Gate/Bottom Contact, BGBC devices) than in staggered structures (i.e. Top Gate/Bottom Contact, TGBC devices). The presence of Schottky barriers, trap states, field dependence of carrier mobility and defected regions near the electrodes have been suggested as the origin of Rc.In this work, the contacts effects in devices with different architectures (staggered and coplanar) will be discussed. Devices characteristics have been measured at different temperature and the results have been analysed by using 2D numerical simulations (fig. 1 and 2). The electrical characteristics of both type of devices can be reproduced considering a Schottky barrier at the source contact with an “effective” barrier lowering, that takes into account different field-dependent effects occurring at the contacts (Shottky effect, tunnelling, trap assisted tunneling) that can increase the current injected by the electrode (fig.1 and 2). In the case of staggered devices, the detailed analysis of the current density shows that, at low Vds and for a given Vgs, the current is mainly injected from an extended source contact region overlapped by the gate electrode, inducing a current spreading along the contact (Ic - current in fig.3). The distribution of the current spreading remains basically constant for increasing Vds up to a value Vdsat1 (fig. 1), when the depletion layer of the Schottky contact expands reaching the insulator-semiconductor interface and causing the pinch-off of the channel at the source end. For Vds>Vdsat1 the current injected from the edge of the source contact rapidly increases (Iedge in fig.3a), due to field enhanced injection mechanisms, while the current injected from the remaining part of the source contact basically saturates. At higher drain voltage (Vds>Vdsat2, see fig.1), pinch off at the drain occurs. In the case of coplanar devices, current spreading, obviously, does not occurs and even at low Vds the current increase is related to the field enhanced injection mechanisms that take place at the edge of the source contact (fig.3b). The lack of the extended contact contribution to the injected current explains the higher contact resistance usually observe in coplanar devices at low Vds compared to staggered OTFTs. On the other hand, at high Vds (saturation condition) higher electric fields are present, in coplanar structure, near the source, that is in direct contact to the channel region. This results in a more efficient carrier injection that allows obtaining an almost ohmic contact condition in coplanar devices in saturation condition.

Flexible Sensors Based on Low-Temperature Polycrystalline Silicon Thin Film Transistor Technology

Flexible sensors are gaining increasing interest in a number of applications, including biomedical, food control, domotics and robotics, having very light weight, robustness and low cost. In order to improve signal-to-noise ratio, integration of readout electronics is crucial and several technologies are available for the fabrication of thin film transistor (TFTs) based circuits on flexible substrates. Among these technologies, the low temperature polycrystalline silicon (LTPS) is particularly attractive, since LTPS TFTs show excellent electrical characteristics, good stability and offer the possibility to exploit CMOS architectures. The different aspects for the direct fabrication of LTPS TFTs on polymer substrates are reviewed and the specific fabrication process adopted on ultrathin polyimide (PI) substrates is described in some detail. In particular, LTPS TFTs were fabricated on ultra-thin PI substrates, deposited by spin-coating on a Si wafer, and excimer laser annealing was used to crystallize the Si. Characteristics electrical parameters are: field effect mobility up to 50 cm2/Vs; threshold voltage of 7 V; on/off ratio >105 . Then, as examples of flexible sensors, we present a tactile sensor for robotic applications and a pH sensor for biomedical applications.The tactile sensors were designed according to the Piezoelectric Oxide Semiconductor Field Effect Transistor (POSFET) structure, enabling sensing and signal conditioning at same site. In this way, it is possible to improve signal to noise ratio and hence the force sensitivity. In our LTPS POSFET devices we adopted as piezoelectric film the polyvinyledenedifluoride –trifluoroethylene P(VDF-TrFE) polymer. The piezoelectric polymer generates a charge on application of a mechanical force which influences the gate bias of the transistor. Gate bias variations, in turn, are directly reflected into drain current variations, that can be further processed by electronic circuits. The measured response to applied forces is linear, as reported in Fig 1a, with a piezoelectric coefficient up to 47 pC/N. The frequency response was tested in the range 30 - 1200 Hz and presented a high-pass behavior (see Fig.1b), according to the adopted common-source bias configuration.The pH sensor was fabricated according to the extended gate structure, as this structure offers many advantages over the conventional ISFET, such as the low cost, simple passivation and package, insensitivity of temperature and light, flexibility of shape of the extended-gate structure, and better long-term stability. The sensitive layer of the extended gate is a nanostructured ZnO film selectively deposited on the Al-gate electrode in a chemical bath at low-temperature. The pH-sensitivity was tested by exposing the extended gate to different pH-solutions and using as a reference electrode an Ag/AgCl electrode. In Fig. 2 the transfer characteristics, measured at low Vds and for different pH-solutions, are reported. In the inset of Fig.2, the threshold voltage shift induced by the pH variation is shown, giving a slope of 59 mV/pH for the pH range 1 – 9, close the ideal Nernstian response. The present results can pave the way to advanced flexible sensing systems, where sensors and local signal conditioning circuits can be integrated on the same flexible substrate.

(Invited) Contact Effects in Organic Thin Film Transistors with Different Device Structures

In this work we discuss the contacts effects in organic transistors with different architectures (staggered and coplanar). By using electrical measurements, performed at different temperatures, and numerical simulations, we show that electrical characteristics of both types of devices can be reproduced considering an effective Schottky barrier and barrier lowering at the source contact. Furthermore, we show that in staggered devices, at low Vds, the current is injected along an extended source contact region, while at high Vds is mainly injected at the edge of the contact, as for coplanar devices. The different architecture also results in different voltage drop at the contact for different drain bias. These differences explain the different contact resistance observed for the two device architectures.

Investigation on the electrical properties of superlattice FETs using a non-parabolic band model

The effect of non-parabolic energy-bands on the electrical properties of an In0.53Ga0.47As/In0.52Al0.48As superlattice FET has been investigated. An energy dependent effective mass was fitted on k·p simulation results and the new band model was implemented into a self-consistent Schrödinger–Poisson solver. This analysis has shown that non-parabolicity effects lead to noticeable changes of the device characteristics with respect the parabolic band model, namely: an increase of the on-state current and a steeper transition from the off- to the on-state sustained across several decades of current, at the expense of an increased off-state leakage. Moreover, the larger density of states in the non-parabolic model causes a 47% growth of the output conductance at low VDS, as well as an increased drain conductance in saturation.

(Invited) Vertical Tunnel FETs Using III-V Nanowire/Si Heterojunctions

Primary purpose in future integrated circuits is to decrease the power consumption while enhancing their performance. In this regard, the reduction of supply voltage of the field-effect transistors (FETs) using high-mobility channels such as III-Vs is effective approach to achieve the power scaling because the power consumption of integrated circuits is to proportional to the square of the supply voltage. With this matter, reduction of off-state leakage current and subthreshold slope (SS, < 60 mV/decade) in FETs is required for decreasing the supply voltage. The use of multi-gate architecture and steep SS transistors such as tunnel FET has been proposed as a way of reducing these parameters.Conventional FETs have a physical limit on SS due to carrier thermal diffusion. Further power scaling of FET will be stopped by the physical limitation even though the mulltigate FETs using III-Vs are used. Thus, steep SS transistors specifically TFET are expected as a promising candidate switch in future energy efficient circuits. The use of the TFETs with an SS of 10 mV/decade with keeping device performance as conventional FETs would reduce the required supply voltage to as low as 0.3 V. Although Si-based TFETs are attractive device for mature Si-CMOS, the Si has low band-to-band tunneling probability, which decreases ON-state current. One of promising materials for increasing the ON-state current of TFETs is a combination of narrow band-gap III-V with a Si, that is, III-V/Si heterojunctions.Our main goal is to replace mature Si-MOSFET by III-V nanowire (NW)-channel and TFET structure using the III-V NW/Si heterojunctions. However, the changes in technology from the mature Si-CMOS to the TFETs using III-V/Si heterojunction present significant challenges in terms of heteroepitaxy, devices processes and so on. Here we report on recent advances in heteroepitaxy of III-V NWs on Si substrate and recent achievements of steep-SS transistor using vertical III-V NW/Si heterojunctions.As for formation of III-V NW-channels on Si, we used selective-area epitaxy with catalyst-free method. Recent progresses in the selective-area growth have enabled integration of vertical III-V NWs on Si substrates with precise positioning [1-3]. These heteroepitaxy provide unique phenomenon at the III-V NW/Si interface in terms of crystallography and electronic property. First, a number of misfit dislocations are decreased with decreasing diameter of the heterojunction [1,4]. Second, the III-V NW/Si with less misfit dislocation inherently forms specific band discontinuity, which is feasible for the utilization of TFETs [5,6]. For example, n-type InAs NWs grown on p-Si substrate has staggered type-II band discontinuity at the InAs/Si interface [6]. And both band-to-band (Esaki) tunneling and Zener tunneling current can be controlled by changing the carrier concentration of p-Si substrate [4]. This is because the position of the Fermi level in p-Si varies the tunneling transport under forward/reverse bias, and means that these III-V NW/Si heterojunctions are feasible as a new junction for TFETs. Thus, we have proposed vertical- and lateral-type TFETs based on III-V NWs/Si heterojunctions [6].As a first step to demonstrate vertical TFET using III-V NW/Si heterojunction with steep SS, high performance gate stacking technologies are required for the III-V NW-channels. We have, therefore, developed device fabrication processes of vertical surrounding-gate architecture using InAs NW [7, 8] and InGaAs NW [9, 10], and achieved very low SS (~ 68 mV/dec.) for InGaAs NW-channel surrounding-gate transistors with EOT = 0.70 nm [11]. Moreover, we proposed high-electron mobility transistor using the InGaAs NW-channel [10] and demonstrate high performance vertical MOSFET using InGaAs NW-channel with transconductance of 1.45 mS/μm at VDS = 0.50 V [11]. The interface state density of the III-V NW/gate-oxide is ranged 2 - 4 ×1012 cm-2eV-1[12], which indicates these device processes and their gate-stacking technologies have good property to elicit steeper SS of vertical TFETs.As for vertical TFET using InAs NW/Si heterojucntion, we have demonstrated much steeper SS ~ 21 mV/dec at room temperature [6]. This was resulted from the increment of heterojunction resistance with decreasing nanowire-diameter and the number of misfit dislocations. And next, we improved the channel resistance for InAs NW-channel by using specific pulse-doping method and revealed that formation of intrinsic InAs NW channel resulted in shifting of turn-on voltage while maintaining steep SS [4]. Other III-V NW/Si heterojunction, such as InGaAs NW/Si junction, has also shown steep turn-on properties under lower VDS[13]. Acknowledgments The authors would like to thank Professors Junichi Motohisa and Tamotsu Hashizume, and Mr. Masatoshi Yoshimura, Eiji Nakai, and Fumiya Ishizaka for the fruitful discussions and the experimental supporting of MOVPE. This work was financially supported by a Grant-in-Aid for Scientific Research from the Ministry of Education, Culture, Sports, Science and Technology (MEXT) and the Japan Science and Technology Agency (JST) PRESTO program.

Current increment of tunnel field-effect transistor using InGaAs nanowire/Si heterojunction by scaling of channel length

We report on a fabrication of tunnel field-effect transistors using InGaAs nanowire/Si heterojunctions and the characterization of scaling of channel lengths. The devices consisted of single InGaAs nanowires with a diameter of 30 nm grown on p-type Si(111) substrates. The switch demonstrated steep subthreshold-slope (30 mV/decade) at drain-source voltage (VDS) of 0.10 V. Also, pinch-off behavior appeared at moderately low VDS, below 0.10 V. Reducing the channel length of the transistors attained a steep subthreshold slope (&amp;lt;60 mV/decade) and enhanced the drain current, which was 100 higher than that of the longer channels.

Fabrication of p-type silicon nanowires for 3D FETs using focused ion beam

A Ga+ focused ion beam (GaFIB) from a FIB/scanning electron microscopy (SEM) dual beam system was used for Si milling and p-type local doping of p+-type silicon nanowires (p+-SiNWs). The resulting p+-SiNWs were then used to create pMOS junctionless nanowire transistor (JNT) prototypes for silicon-on-insulator wafer substrates. The electron beam from the FIB/SEM dual beam system was used to deposit SiO2 gate dielectric and Pt source/drain electrodes for JNT transistors. Width, length, and height dimensions of p+-SiNWs were approximately 35 nm, 6 μm, and 15 nm, respectively, and the JNT gate length was 1 μm. Finally, photolithography, Al sputtering deposition, and lift-off processing were conducted to define the Al gate electrode and contacts on Pt source/drain electrodes. Energy dispersive x-ray spectroscopy measurements were taken to confirm the surface composition of p+-SiNWs and Ga doping. Drain–source current (IDS) versus drain–source voltage (VDS) measurements of JNT transistors indicated that the device is working like a JNT device (gated resistor). The authors noted high resistance on Al/Pt source and drain electrodes, which leads to distortions on IDS versus VDS curves as non-ohmic electrical contact for low VDS signal. However, these distortions can be reduced with a longer contact sintering process or by increased p+-SiNW doping. Our conclusions indicate that utilizing a GaFIB/SEM dual beam system for Si milling, Ga doping, and SiO2 and Pt depositions can be a favorable alternative for fabricating junctionless devices based on p+-SiNWs.

Extraction of Channel Electron Effective Mobility in InGaAs/Al $_{\bf 2}$O$_{\bf 3}$ n-FinFETs

A compact set of equations based on the multiple subbands quasi-ballistic transport theory is developed, and is used to investigate the channel electron effective mobility in recently reported In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> tri-gate n-FinFET. The extracted electron effective mobility μn is around 370 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> bias at room temperature and decreases with increasing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> , and increases with increasing temperature (240-332K). It is very different from the case of Si n-MOSFETs, where the electron mobility decreases with increasing temperature. The low channel effective mobility and the ab-normal temperature dependence of μ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</sub> are ascribed to the high acceptor interface trap and border trap energy densities in the conduction band energy of InGaAs. The ballistic channel resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ball</sub> at low Vds is calculated and compared with the measured channel resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub> . The low transmission coefficient T = R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ball</sub> /R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CH</sub> ≈ 0.06 to 0.05 indicates that there is a large room to improve the InGaAs/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> n-FinFET performance.

Electrical and structural dependence of operating temperature of AlGaN/GaN HEMTs

Understanding the distribution of the considerable heat generated in the active region of high power AlGaN/GaN high electron mobility transistors (HEMTs) at the sub-micron length scales relevant to the failures being observed in these devices is crucial for understanding device performance and reliability. In addition, electrical bias conditions and structural characteristics such as field plates alter the electric field distribution and thermal path within the device leading to changes in the heat generation profile across the channel. This in turn influences the value and location of the device peak temperature and the channel to ambient (or case or base-plate) thermal resistance. The channel temperature distribution of AlGaN/GaN HEMT structures with and without source connected field plates were examined via micro-Raman spectroscopy and coupled electro-thermal simulation. For both type of structures, high Vds conditions lead to significantly higher channel temperature compared to that for low Vds conditions for the same power dissipation level. This is important because the industry standard Arrhenius relation assumes the total power is sufficient to describe the device channel temperature and that the bias condition is irrelevant [1]. We explore the level of agreement between modeling and experiment, and also the extent to which variability in input parameters for the modeling affects model results. We show that operating bias condition has a significant role in device reliability by altering value and location of the peak temperature, which then alters the type and rate of thermally induced degradation taking place at critical locations such as the drain side corner of the gate. Specifically, care must be taken when extrapolating results of an accelerated life test to usage conditions at dissimilar bias conditions to consider if the results will be applicable.

The Impact of Bias Conditions on Self-Heating in AlGaN/GaN HEMTs

The thermal response of AlGaN/GaN high electron mobility transistors directly correlates with the overall performance and reliability of these devices. In general, a hot spot develops near the drain end of the gate electrode during power dissipation. The device channel temperature was examined via micro-Raman spectroscopy under various bias conditions where power dissipation levels were identical. Under these bias conditions, difference in internal states (sheet carrier density and electric held distribution) within the device alters the heat generation profile across the channel. High Vds conditions lead to significantly higher channel temperature compared to that for low Vds conditions although the power dissipation is kept constant. Experimental results show ~13°C deviation between Vds = 45 V and Vds = 7 V cases when the power dissipation is 4.5 W/mm. This suggests that bias conditions may have a relatively signihcant impact on device reliability and that this effect must be considered when building thermal models of devices under operation or undergoing accelerated life testing.

Current spreading effects in fully printed p-channel organic thin film transistors with Schottky source–drain contacts

Contact effects have been analyzed, by using numerical simulations, in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source/drain contacts. Considering source–drain Schottky contacts, with a barrier height of 0.46eV, device characteristics can be perfectly reproduced. From the detailed analysis of the current density we have shown that current spreading occurs at the source contact, thus influencing the effective contact resistance. At low Vds and for a given Vgs, the current is mainly injected from an extended source contact region and current spreading remains basically constant for increasing Vds. However, by increasing Vds the depletion layer of the Schottky contact expands and reaches the insulator–semiconductor interface, causing the pinch-off of the channel at the source end (Vdsat1). For Vds>Vdsat1 the current injected from the edge of the source contact rapidly increases while the current injected from the remaining part of the source contact basically saturates. Current spreading shows a Vgs-dependence, since the contact injection area depends on the channel resistance and also barrier lowering of the Schottky source contact depends upon Vgs. The injected current from the edge of the source contact can be reproduced using the conventional diode current expression, assuming a constant value for the zero barrier lowering saturation current and considering a Vgs-dependent barrier lowering. The presented analysis clarifies the Vgs-dependence of the contact current–voltage characteristics and points out that the I–V contact characteristics cannot directly be related to a single diode characteristics. Indeed, the contact characteristics result from the combination of two rather different regimes: at low Vds the current is injected from an extended source contact region with a current spreading related to Vgs, while for Vds above the pinch-off of the channel at source end, the current is injected primarily from the edge of the source contact and is strongly enhanced by the barrier lowering.

Double-Peak N-Shaped Negative Differential Resistance in a Quantum Dot Field Effect Transistor

Double-peak N-shaped negative differential resistance (NDR) with a high peak-to-valley ratio is observed in the output characteristics of a GaAs-based modulation-doped field effect transistor with InAs quantum dots in the barrier layer (QDFET). One NDR peak with a higher source-drain voltage VDS is explained as the real-space transfer (RST) of high-mobility electrons in the channel into the quantum dots layer, while the other with a lower VDS is caused by the high-mobility RST electrons in the channel into the modulation-doped AlGaAs barrier layer on the other side. We depict a point how a thinner Schottky barrier layer provides a stronger potential, opening a possibility of two-directional channel electron transfer when a much higher VG is applied. The result suggests that the QDFET can be an attractive candidate for high-speed logic application and memory devices.

Scaling behaviors of transient noise current in organic field-effect transistors

Top-contact and bottom-gate organic field-effect transistors (OFETs) based on poly(3-hexylthiophene), P3HT polymer has been fabricated with thermal treatment condition. Transient noise currents of the OFETs are measured at various source–drain voltages ranging from 0V to −60V with respect to a fixed gate voltage of −60V. The results from conventional power spectral density method are compared with the more robust Detrended Fluctuation Analysis. The latter has been proven to be reliable for fractal signals particularly in the presence of nonstationary effects. Interesting transitions between multiscaling and monoscaling behaviors are observed in the power spectral density as well as the Detrended Fluctuation Analysis plots for different applied source–drain voltage Vds. Uncorrelated white noise characteristics are observed for noise current measured at low Vds, meanwhile 1/f noise-like scaling behaviors are observed at intermediate Vds. At higher Vds, the noise characteristics appeared to be close to Brownian-like power-law behavior. The scaling characteristics of the transient noise current can be related to the charge carrier dynamics. It is also found that large numbers of trap centers are induced when the device is stressed at high applied Vds. The existence of these trap centers would disperse charge carriers, leading to 1/f type noise that could diminish the presence of Brownian noise in a very short time.

Intrinsic parameter extraction of a-InGaZnO thin-film transistors by a gated-four-probe method

We analyzed the intrinsic electrical characteristics of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) using a gated-four-probe method. Based on the back channel potential, the extraction of intrinsic field-effect mobility (μFEi) and parasitic resistance in source (Rs) and drain (Rd) electrodes was performed especially for low VGS and VDS conditions. The resulting μFEi showed typical VGS dependency of amorphous semiconductor TFTs. However, Rs and Rd showed that there can be non-uniformity in source/drain parasitic resistance, which indicates that a separate analysis of the parameters of each electrode is essential for further improvement of the performance of a-IGZO TFTs.

On the high-field transport and its temperature dependence in deca-nanometer fully depleted silicon-on-insulator field-effect-transistor

Low-temperature characterization has been performed on fully depleted silicon-on-insulator (FDSOI) field-effect-transistor (FET) with gate length (Lg) down to 25 nm to clarify transport mechanisms that determine device performance in deca-nanometer scale. Linear drain current of FDSOI FET follows Lg−1 scaling down to 25 nm Lg, where mobility dominates, while saturation drain current largely deviates from Lg−1 scaling. Temperature dependence of effective source velocity at high drain voltage (Vds) is weaker than that at low Vds in short Lg and is consistent with that of saturation velocity. Drift velocity measurement revealed velocity overshooting behavior at high lateral field, indicating further Lg scaling benefit.

Threshold voltage degradation under high Vgs and low Vds on 200 V SOI power devices

The hot-carrier degradation behavior of the 200V lateral insulated gate bipolar transistor and lateral diffused MOS transistor both on SOI substrates (SOI-LIGBT and SOI-LDMOS) under high Vgs and low Vds is experimentally investigated. It is shown that the hot electron injection and trapping into gate oxide in the channel region will domains the degradation, which results in the positive threshold voltage (Vth) shift, however, it is very interesting that the degradation level in SOI-LIGBT device is much more serious than that in SOI-LDMOS device. Finally, an improved method to reduce the Vth degradation of SOI-LIGBT is also presented, which is adding a P-type buried layer under the source to change the hole current path. All the results have been verified by MEDICI simulations.

Copper source/drain electrode contact resistance effects in amorphous indium–gallium–zinc‐oxide thin film transistors

AbstractThis paper focuses on the viability of low‐resistivity electrode material (Cu) for source/drain electrodes in thin film transistors (TFTs). The effective resistances between Cu source/drain electrodes and amorphous indium gallium zinc oxide (a‐IGZO) thin‐film transistors were examined. Intrinsic TFT parameters were extracted by the transmission line method (TLM) using a series of TFTs with different channel lengths measured at a low source/drain voltage. The TFTs fabricated with Cu source/drain electrodes showed good transfer characteristics with a field‐effect mobility of 9.64 cm2/Vs, and good output characteristics with steep rise in the low VDS region. (© 2009 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)