The problem to identify the SHE through DC measurements occur due to the superposition of this effect with the channel length modulation (λ). As presented in Figure 1, depending on the thermal resistance (Rth), the classical negative output conductance may not be observed at all if λ > 0, inducing one to wrongly believe that no SHE is present. The transistor efficiency (gm/ID) method was initially proposed to allow a fast verification of whether the self-heating effect (SHE) is present in the device being studied [1]. This method allows for an easier visualization and qualitative characterization of the SHE, as represented in Figure 2, separating the effect in different regions of intensity; however, it would not be possible to use it to compare different devices. Since the method originally used the drain current (ID) on the x-axis with fixed gate voltage (VGS) and varying drain voltage (VDS), imprecise comparisons would be performed if the devices being studied were differently affected by the λ, as shown in Figure 3. Simple mathematical simulations were performed in order to obtain these results, in which the λ was considered through the model ID = IDsat.(1 + λ.VDS), where IDsat is the saturation current at low VDS, and λ is a fitting parameter. From Figure 3, one might wrongly conclude that the devices with greater λ present a weaker SHE, when in fact the opposite should be truth, since ID increases with λ, resulting in more heat being generated, thus stronger SHE. To achieve an improvement to the method, a new analysis of the expression for the influence of the SHE on the gm/ID in saturation must be conducted. Therefore, it is presented in (1), where T0 is the room temperature, c-factor is the mobility degradation coefficient with temperature, VGT is the overdrive voltage (VGT = VGS – Vt, Vt is the threshold voltage), and θ is the electric field mobility degradation factor. The terms multiplying the thermal resistance (and consequently relevant to the SHE) are both ID and VDS, thus, initially either of them could be used as a variable for the analysis. Nevertheless, as previously explored, the use of ID with varying VDS would be problematic due to λ influence. Considering that VGT influences ID, it could be employed; however, given the degradation of the mobility due to the vertical electrical field, observed in (1) as the θ factor, the use of VGT becomes less interesting. Hence, the only option remaining is the direct use of VDS as the variable on the x-axis. To verify if the use of this option presents relevant results, Figure 4 was generated from simulations like those of Figure 1. In this case, it is possible to observe that, the greater the gm/ID degradation from the expected plateau in the case where Rth = 0 K/W, the more significant is the SHE. An important consideration that must be made concerning the use of this method for comparisons is that the θ factor could still add another undesired component to the SHE analysis on the gm/ID curves. Should the comparison be performed among devices fabricated in multiple dimensions or even distinct technologies, factors that might result in different θ, the gm/ID in saturation for each device will change, despite presenting a similar degradation, becoming lower for higher values of θ, even though the Rth is kept constant, as shown in Figure 5. To improve the comparison, a simple mathematical fix is suggested, resulting on the curves present in Figure 6, where each is divided by the factor F = [2/VGT – θ/(1+θ.VGT)]. In this case, the agreement for the same Rth is much better, ensuring that the SHE becomes the main factor in the degradation of the gm/ID, as demonstrated by varying Rth. To verify these results, experimental pFinFET devices were measured and had their gm/(ID*F) plotted as a function of VDS, after applying the division by F, resulting in Figure 7. As expected, the device with shorter channel presents a higher gm/ID degradation due to the SHE, since it has a higher current level than the other devices. This approach for SHE observation through DC measurements using the transistor efficiency improvement is presented in this paper for the first time. Figure 1
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Feb 23, 2024
Haijun Lou + 3
Open Access