Low Thermal Budget Research Articles

Low Thermal Budget Reconfigurable Fully Depleted Silicon on Insulator Field-Effect-Transistors With Embedded Boolean Logic

We report the low thermal budget reconfigurable fully depleted silicon on insulator (FDSOI) field-effect-transistors, focusing on the management of the fabrication thermal budget, toward three-dimensional integration and the further improvement of the circuit functionality. This is realized using atomic layer deposition tool-enabled O2/NH3 plasma surface passivation technology and long duration thermal procedure. Moreover, such front-gated FDSOI reconfigurable field effect transistors (RFETs) gain the embedded Boolean logic of “AND” and “NOR” in N and P-type modes, respectively. This strategy has the potential to be a key enabler for functional improvement in the nanoscale hyper-scaling era.

Rapid photonic curing effects of xenon flash lamp on ITO–Ag–ITO multilayer electrodes for high throughput transparent electronics

High-throughput transparent and flexible electronics are essential technologies for next-generation displays, semiconductors, and wearable bio-medical applications. However, to manufacture a high-quality transparent and flexible electrode, conventional annealing processes generally require 5 min or more at a high temperature condition of 300 °C or higher. This high thermal budget condition is not only difficult to apply to general polymer-based flexible substrates, but also results in low-throughput. Here, we report a high-quality transparent electrode produced with an extremely low thermal budget using Xe-flash lamp rapid photonic curing. Photonic curing is an extremely short time (~ μs) process, making it possible to induce an annealing effect of over 800 °C. The photonic curing effect was optimized by selecting the appropriate power density, the irradiation energy of the Xe-flash lamp, and Ag layer thickness. Rapid photonic curing produced an ITO–Ag–ITO electrode with a low sheet resistance of 6.5 ohm/sq, with a high luminous transmittance of 92.34%. The low thermal budget characteristics of the rapid photonic curing technology make it suitable for high-quality transparent electronics and high-throughput processes such as roll-to-roll.

High mobility amorphous InSnO thin film transistors via low-temperature annealing

In this article, we fabricated amorphous InSnO thin film transistors (TFTs) with exceedingly high mobility and low thermal budget. The device is annealed only at a low temperature of 150 °C, a field-effect mobility (μFE) of 70.53 cm2/V s, a subthreshold swing of 0.25 V/decade, an on/off current ratio over 108, and a reasonable threshold voltage shift under negative bias stress. The influence of thermal annealing on amorphous InSnO TFTs was investigated by systematically analyzing the crystallization, surface morphology, internal chemical state, and energy band relationship of the InSnO thin film. Amorphous InSnO films deposited at room temperature have a sparse and porous loose structure, which has carrier scattering caused by poor film quality, resulting in low mobility and few free carriers in the film. With the increase in the annealing temperature, the In and Sn metal cations are further oxidized, increasing the carrier concentration in the film and forming a dense M–O–M network when annealed at 150 °C. With the further increase in the annealing temperature, a large number of thermally excited free electrons make the device appear metal like conductivity. This paper expands the research on a high electron concentration InSnO material as the active layer and promotes the development of amorphous oxide semiconductors in high mobility and flexible TFTs.

Highly Si‐Doped GaN Regrown by Metal–Organic Vapor‐Phase Epitaxy for Ohmic Contact Applied to Quaternary Barrier‐Based High‐Electron‐Mobility Transistors

The quaternary barrier InAlGaN is suitable for GaN high‐electron‐mobility transistors (HEMT) power microwave applications. High doping of the semiconductor under the drain and source is a known suitable solution to achieve low ohmic contact resistance. However, InAlGaN quaternary alloys require a low thermal budget to avoid indium desorption from the active layer during regrowth and thus deteriorating the barrier. Herein, a selective‐area growth technique at 850 °C by metal–organic vapor‐phase epitaxy (MOVPE) to achieve low contact resistance with respect to temperature constraint is presented. Regrowth temperature and mask geometry are investigated to achieve selectivity and control of the regrowth rate. The use of H2 as carrier gas decomposes the GaN buffer layer and damages the surface, creating material cluster during regrowth. Growth with N2 carrier gas shows nonselective epitaxy, as there are deposits on the entire surface of the dielectric mask. Switching from one carrier gas to another depending on the step in the MOVPE reactor helps to control both the morphology and selectivity. The resulting high doping levels of 8 × 1019 cm−3 lead to a low contact resistance of 0.26 Ω mm.

Crystallization of high gyrotropy garnets with decreasing thermal processing budgets as analyzed by electron backscatter diffraction

Rare-earth iron garnets with large magnetic gyrotropy, made with reduced thermal budgets, are ideal magneto-optical materials for integrated isolators. However, reduced thermal budgets impact Faraday rotation by limiting crystallization, and characterization of crystallinity is limited by resolution or scannable area. Here, electron backscatter diffraction (EBSD) is used to measure crystallinity in cerium substituted yttrium- and terbium-iron garnets (CeYIG and CeTbIG) grown on planar Si, crystallized using one-step rapid thermal processes, leading to large Faraday rotations > −3500 °/cm at 1550 nm. Varying degrees of crystallinity are observed in planar Si and patterned Si waveguides, and specific dependences of crystallite size are attributed to the nucleation/growth processes of the garnets and the lateral dimensions of the waveguide. On the other hand, a low thermal budget alternative–exfoliated CeTbIG nanosheets–are fully crystalline and maintain high Faraday rotations of −3200 °/cm on par with monolithically integrated thin film garnets.

Chitosan-gated organic transistors printed on ethyl cellulose as a versatile platform for edible electronics and bioelectronics.

Edible electronics is an emerging research field targeting electronic devices that can be safely ingested and directly digested or metabolized by the human body. As such, it paves the way to a whole new family of applications, ranging from ingestible medical devices and biosensors to smart labelling for food quality monitoring and anti-counterfeiting. Being a newborn research field, many challenges need to be addressed to realize fully edible electronic components. In particular, an extended library of edible electronic materials is required, with suitable electronic properties depending on the target device and compatible with large-area printing processes, to allow scalable and cost-effective manufacturing. In this work, we propose a platform for future low-voltage edible transistors and circuits that comprises an edible chitosan gating medium and inkjet-printed inert gold electrodes, compatible with low thermal budget edible substrates, such as ethylcellulose. We report the compatibility of the platform, characterized by critical channel features as low as 10 μm, with different inkjet-printed carbon-based semiconductors, including biocompatible polymers present in the picogram range per device. A complementary organic inverter is also demonstrated with the same platform as a proof-of-principle logic gate. The presented results offer a promising approach to future low-voltage edible active circuitry, as well as a testbed for non-toxic printable semiconductors.

Analysis of the Annealing Budget of Metal Oxide Thin‐Film Transistors Prepared by an Aqueous Blade‐Coating Process

AbstractMetal oxide (MO) semiconductors are widely used in electronic devices due to their high optical transmittance and promising electrical performance. This work describes the advancement toward an eco‐friendly, streamlined method for preparing thin‐film transistors (TFTs) via a pure water‐solution blade‐coating process with focus on a low thermal budget. Low temperature and rapid annealing of triple‐coated indium oxide thin‐film transistors (3C‐TFTs) and indium oxide/zinc oxide/indium oxide thin‐film transistors (IZI‐TFTs) on a 300 nm SiO2 gate dielectric at 300 °C for only 60 s yields devices with an average field effect mobility of 10.7 and 13.8 cm2 V−1 s−1, respectively. The devices show an excellent on/off ratio (>106), and a threshold voltage close to 0 V when measured in air. Flexible MO‐TFTs on polyimide substrates with AlOx dielectrics fabricated by rapid annealing treatment can achieve a remarkable mobility of over 10 cm2 V−1 s−1 at low operating voltage. When using a longer post‐coating annealing period of 20 min, high‐performance 3C‐TFTs (over 18 cm2 V−1 s−1) and IZI‐TFTs (over 38 cm2 V−1 s−1) using MO semiconductor layers annealed at 300 °C are achieved.

Cold spray-based rapid and scalable production of printed flexible electronics

Flexible electronics (FE) is attracting great attention from both scientific and industrial communities, and plays a crucial role in smart device applications. Despite great promise, traditional printing approaches ( e.g. , screen printing, ink-jet printing, etc.) often need a high-temperature post-sintering process to produce FE with desired electrical conductivity and adhesion strength. The post-sintering processes, however, often lead to fast oxidation of the functional coating while limiting the use of low-thermal budget substrates. Exponential advance of FE in a large-scale and energy-efficient manner relies on rationally eliminating the post-sintering processes. To this end, with the aim of uncovering process-structure-properties relationships, we employ the emerging cold spray (CS) technique for rapid and scalable production of FE without a need for high-temperature post-sintering. In this regard, micron-scale Tin (Sn) particles are directly written on a flexible polymer substrate (PET) by cold spraying under ambient conditions. The effect of CS process parameters on the resultant coatings is comprehensively characterized in terms of microstructure, film thickness, electrical conductivity, linewidth, and adhesion strength. The resulting electrodes show excellent electrical conductivity (6.98×10 5 S.m -1 ), adhesion strength, long-term stability, and flexibility without significant conductivity loss after 1,000 bending cycles. By leveraging the CS operational settings, a resistive macro-heater (12×15 cm 2 ) and an LED circuit (2.5 cm×18 cm) are fabricated to demonstrate the applicability of the CS in printed FE. Moreover, to address the low-spatial resolution of CS writing, a case study on sequential CS and femtosecond laser machining is performed, which further led to ultra-high resolution ( i.e. , 30 µm linewidth) custom-designed flexible electrodes. Thus, the present study reveals the immense potential of the CS technique for rapid and scalable production of FE without the need for post-sintering. • Cold spray deposition is employed in printed flexible electronics (FE). • Tin (Sn) particles are directly written on a flexible substrate (PET) at ambient conditions. • Flexible electrodes with excellent electrical conductivity (6.98×10 5 S.m -1 ) are achieved. • The resultant electrodes are constructed into FE applications such as a resistive heater. • Cold spray is found to be promising for rapid and scalable production of printed FE.

Robust low-temperature (350 °C) ferroelectric Hf0.5Zr0.5O2 fabricated using anhydrous H2O2 as the ALD oxidant

In this Letter, the robust ferroelectric properties of low-temperature (350 °C) Hf0.5Zr0.5O2 (HZO) films are investigated. We demonstrate that the lower crystallization temperature of HZO films originates from a densified film deposition with an anhydrous H2O2 oxidant in the atomic layer deposition process. As a consequence of this densification, H2O2-based HZO films showed completely crystallinity with fewer defects at a lower annealing temperature of 350 °C. This reduction in the crystallization temperature additionally suppresses the oxidation of TiN electrodes, thereby improving device reliability. The low-temperature crystallization process produces an H2O2-based HZO capacitor with a high remanent polarization (Pr), reduced leakage current, high breakdown voltage, and better endurance. Furthermore, while an O3-based HZO capacitor requires wake-up cycling to achieve stable Pr, the H2O2-based HZO capacitor demonstrates a significantly reduced wake-up nature. Anhydrous H2O2 oxidant enables the fabrication of a more reliable ferroelectric HZO device using a low process thermal budget (350 °C).

The ultra-thin AlN epitaxy on monolayer WS2 by helicon sputtering at 400 °C

This work demonstrates the epitaxial growth of ultra-thin AlN films grown on monolayer WS2/Sapphire by helicon sputtering. In our work, WS2 acts as a template to facilitate the initial two-dimensional (2D) AlN growth via van der Waals epitaxy (VDWE), and this growth method provides a promising semiconductor manufacturing process with low thermal budget (<450 °C) than the required for the backend-of-the-line (BEOL). The ultrathin AlN epitaxy on WS2 is characterized by synchrotron-based grazing-incidence wide-angle x-ray scattering (GIWAXS). There are two stages in AlN epitaxy on the WS2; the first is the layered AlN growth aligned with the underlying WS2 lattice. The subsequent development of AlN transforms into 3D growth, which is similar to Stranski–Krastanov (SK) mode. The ultrathin AlN films achieve atomic level smoothness and significant piezoelectric properties as indicated by the technique of atomic- and piezo force microscopy (AFM/PFM). This research broadens the application of 2D materials in assisting AlN epitaxy and has a potential avenue for hetero-epitaxial integration in developing future electronic devices.

N-buffer design and optimization in 4500V class IGBT

In this paper, the effects of doping structure of multi-proton injection (MPI) buffer layer on static and short circuit characteristics of IGBT were studied, and the relationship between donor concentration of the buffer layer and injection dose and annealing temperature was studied. The MPI buffer layer suitable for 4500V IGBT was optimized by comparative experiments. This MPI buffer layer can solve the problem of high-temperature activation of the traditional IGBT buffer layer and lower thermal budget and can be fabricated on large wafers for better parameter consistency.

Electrical Performance of 28 nm-Node Varying Channel-Width nMOSFETs under DPN Process Treatments.

The decoupled-plasma nitridation treatment process is an effective recipe for repairing the trap issues when depositing high-k gate dielectric. Because of this effect, electrical performance is not only increased with the relative dielectric constant, but there is also a reduction in gate leakage. In the past, the effect of nitridation treatment on channel-length was revealed, but a channel-width effect with that treatment was not found. Sensing the different nano-node channel-width n-channel MOSFETs, the electrical characteristics of these test devices with nitridation treatments were studied and the relationship among them was analyzed. Based on measurement of the VT, SS, Gm, ION, and IOFF values of the tested devices, the electrical performance of them related to process treatment is improved, including the roll-off effect of channel-width devices. On the whole, the lower thermal budget in nitridation treatment shows better electrical performance for the tested channel-width devices.

Plasmon-coupled sub-bandgap photoluminescence enhancement in ultra-wide bandgap CuO through hot-hole transfer

Ultra-wide bandgap oxide semiconductors are garnering widespread interest for numerous applications, including high-power electronics, deep-UV opto-electronics, quantum devices, and applications in hostile environments. CuO has recently been shown to be a good contender for ultra-wide bandgap oxide materials. CuO's ultra-wide bandgap property is still in its infancy as far as scientific understanding is concerned. Herein, sub-bandgap emission properties of ultra-wide bandgap CuO thin films, deposited using a facile and low-thermal budget solution-process have been systematically investigated using temperature-dependent photoluminescence measurements. Interestingly, near-infrared (NIR) emission has been observed in ultra-wide bandgap CuO with sub-bandgap (488 nm) excitation suggesting involvement of defect and tail states in emission properties. Further, with the incorporation of Au nanoparticles, four-fold enhancement in the NIR emission was observed. Temperature dependent photoluminescence measurements have suggested enhanced Purcell effect in Au and CuO. The enhanced NIR emission can be assigned concertedly to metal-enhanced fluorescence, plasmon-coupling with photoluminescence and hot-carrier transfer from the metal. Time-resolved photoluminescence measurements have shown clear change in the emission dynamics with Au coating (decay time changed from 7.6 ns to 3 ns). Further, systematic DFT studies have been performed to clearly understand the effect of defects on the emission and absorption properties of ultra-wide bandgap CuO. Finally, the effect of Au on other optical and electrical features has been studied using electron paramagnetic resonance measurements and current-voltage characteristics. This study will expand the understanding of the optical and electrical properties of ultra-wide bandgap CuO for better performing optoelectronic devices.

Investigation of Arsenic Transient Enhanced Diffusion From Emitter Process at 550 °C Si:As RP-CVD Epitaxy Using Disilane Precursor

Reduced Pressure Chemical Vapor Deposition (RP-CVD) Epitaxy bellow 600 °C is studied for 3D sequential integration [1] where cyclic deposition is needed. Another approach can be useful with Si epitaxy at temperature bellow 600 °C : the deposition of amorphous Si on dielectric during non-selective epitaxy combined with solid phase epitaxy regrowth (SPER) to extend the monocrystalline area. Indeed, using temperature above 600 °C during non-selective epitaxy, a polycrystalline Si film is formed on dielectric. This technique has been used in heterojunction bipolar transistor for the non-selective base deposition [2] and can also be used to ensure a fully monocrystalline emitter.Si:As process has been developed at 550 °C using disilane (Si2H6) as Si precursor and Arsine (AsH3) for As precursor. At this temperature, disilane is mandatory to ensure a sufficient growth rate. The disilane process will be compared to a process of reference, using silane (SiH4) precursor at 620 °C. The As dopant concentration targeted is between 1x20 at.cm-3 and 5x20 at.cm-3. Finally, the dopant diffusion is controlled on non-productive Si(100) wafer (NPW), without pattern, by SIMS for both processes before and after thermal budget (720 °C, 1 h + high temperature Spike anneal) to simulate the thermal budget undergone by the emitter.Thanks to the ASTAR system [3] from NanoMEGAS, the crystal orientation and phase maps of the emitter are extracted for both processes (Fig 1.a). ASTAR system is based on the Automated Crystal Orientation Mappings technique used on a Transmission Electron Microscope (ACOM-TEM). With silane precursor, a poly-emitter is generated whereas the emitter is fully monocrystalline with disilane. The amorphous deposition coupled with SPER ensure a fully monocrystalline emitter. SIMS analysis have been performed and show abnormal diffusion of As with disilane process. To understand the causes of the diffusion, both Si:As processes have been reproduced on NPW by full sheet epitaxy. The abnormal diffusion is still observed with the disilane process (Fig 1.b). Compared to diffusion length extracted from [4] (19nm) the diffusion of As is enhanced. Moreover, As enhanced diffusion occurs for low temperature thermal budget (Fig. 1.c).Historically, defects generated from implantation are known to enhance the diffusion length of the dopant. This phenomenon is called Transient Enhanced Diffusion (TED) and it has been studied and observed from dopant implantation [5]. The implantations generate a supersaturation of interstitials defects (such as auto-interstitial) which enhance the dopant diffusion for low temperature thermal budgets. This is a transient effect because the enhanced diffusion occurs in a short time [5]. In our case, several anneal at 720 °C were applied on the disilane Si:As layer from 1 h to 24 h (Fig. 1.d). Most of the diffusion occurs after the annealing at 720 °C, 1 h. These results highlight the transient effect of the As diffusion using disilane process. With the disilane process, TED of As occurs. Indeed, enhanced diffusion of Arsenic appears only for low temperature annealing and the effect is also transient. Compared to implantation which generates defects during the bombardment, low temperature epitaxy generates defects when the growth rate is too high. The molecules from the gas phase are adsorbed on the surface and break down on atoms (called adatom). The adatoms diffuse on the surface to find a suitable site. During low temperature epitaxy, when the growth rate is too high, the adatom don’t have enough time to diffuse on a suitable site and generate defects.Finally, dopant profile analysis will be completed by atomic force microscopy (AFM) and sheet resistance measurement. The AFM will provide an evolution of the surface topography with the annealing. The sheet resistance, coupling with SIMS, will help to extract the deactivation of dopant. The causes of the TED from disilane process at 550 °C will be discussed and experimental results will be provided.[1] L. Brunet et al., IEEE International Electron Devices Meeting (IEDM), 2018[2] Holger Rücker and Bernd Heinemann, Semicond. Sci. Technology, 2018[3] A. Valery, Doctoral dissertation. Université Grenoble Alpes, 2017[4] S. W. Jones, "Diffusion in silicon". IC Knowledge LLC, 2008[5] S. C. Jain, et al., Journal of applied physics, 2002 Figure 1

(Digital Presentation) Properties of Selectively Grown Si:P Layers below 500°C for Use in Stacked Nanosheet Devices

With the introduction of novel stacked CMOS transistor integration schemes such as sequential 3D and CFETs [1,2], there is an increasing need for highly active source/drain layers with a low overall thermal budget. For some integration schemes, processing temperatures below ~ 525°C are desired [3] and in most cases, the contacts need to be formed on the {110} surfaces of exposed Si nanosheets. In this paper, we report on selectively grown Si:P layers below 500°C targeting application in stacked nanosheet-based devices. In contrast to conventional approaches where selectivity is obtained at low temperatures using Cyclic-Deposition and Etch (CDE) with HCl/GeH4 as an etchant [4,5], we rely for this work on Cl2-based etching in combination with Si3H8 as a high-order Si precursor [6]. The Si:P layers were grown in a 300 mm ASM Intrepid® ES reduced pressure chemical vapor deposition reactor on Si (001) substrates.Figure 1 shows some typical characteristics for the Si:P layers without etching (“Dep-only”) and CDE Si:P layers below 500°C. As the temperature is lowered, the growth rate and P incorporation for a given PH3 flow decreases substantially, while the active concentration increases. For both the “Dep-only” and CDE layers, a minimum develops in the resistivity which corresponds to a maximum in active concentration as derived from micro-Hall measurements. Due to the etching during CDE, a P-enrichment takes place and the P concentration in the layers is enhanced compared to the “Dep-only” case. A minimum resistivity of 0.28 mOhm.cm (Pact ~ 6e20/cm3) is obtained for CDE at 480°C which is slightly larger than the minimum resistivity of 0.24 mOhm.cm (Pact ~ 1e21/cm3) for the “Dep-only” case at the corresponding temperature.Figure 2 shows the application of the CDE process on wafers with fins. By lowering the deposition time at a constant etching time per cycle, a (wafer-scale) selective regime can be reached. For the “Dep-only” case, quite some defects and nuclei are present on the sidewalls of the Si-fins and the oxide dielectric, respectively, which are finally removed by sufficient Cl2 etching.Figure 3 compares the corresponding X-TEMs of the above fins after “Dep-only” and selective CDE conditions. For the “Dep-only” case we can only observe a mono-crystalline growth in the <100> direction. For other growth directions like <110>, epitaxial breakdown-down occurs resulting in a substantially reduced crystalline thickness. With the use of Cl2 based CDE, a selective growth can be reached as well as a clear structural improvement in the <110> growth direction, which is very important for the application in nanosheet devices. Finally, once a (111) facet is formed, twin defects occur as expected for low temperature Si:P and Si:C:P [7].The growth behavior of the CDE processes in relevant nanosheet geometries is currently under investigation.

Gesn Bonding Technology for Integrated Laser-on-Chip Photonics

With the numerous recent demonstrations of germanium-tin (GeSn) semiconductor lasers, this material has become the strongest candidate for the realization of photonic-integrated circuits (PICs). However, the high defect density of this material often results in high lasing thresholds, making them undesirable for real-world applications. Furthermore, the low-thermal budget of high Sn content (>9 at.%) GeSn makes it exceptionally hard to grow onto other materials without introducing point defects. Herein, we present a novel method of directly combining GeSn with other materials through low-temperature wafer bonding. Through this technique, we can reduce the harmful high defect density and improve the lasing performance. To cater to the low thermal budget, we optimized the bonding processes which is critical in preventing Sn segregation to the surface. Through this method, we provide compelling evidence for the enhancement in photoluminescence in GeSn. Additionally, this technique can be extended to fabricate new material stacks, presenting unforeseen opportunities in other fields such as non-linear photonics.

Impact of the Low Temperature Ohmic Contact Process on DC and Forward Gate Bias Stress Operation of GaN HEMT Devices

In AlGaN/GaN high electron mobility transistors (HEMTs), high temperature processes (such as ohmic annealing with >800°C value) could deform the crystal structure and induce trap states within the bulk and surface. Expanded defect densities cause crucial problems, such as threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{V}_{\text {th}}$ </tex-math></inline-formula> ) instability, current collapse, and high leakages. In this work, a low temperature ohmic contact process (630°C, 10 minutes) is adopted with recess etch, and contact resistances <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$&lt; 0.1\Omega ~\cdot $ </tex-math></inline-formula> mm with low sheet resistances are achieved. The positive impact of this low thermal budget process on surface morphology, DC operation, long-term stability, and forward gate bias stress of the device is studied.

Advances in In-situ Boron and Phosphorous Doping of SiGeSn

Dopant concentrations higher than 1x1019 cm-3 are required to improve the performances of various GeSn based devices such as photodetectors, electrically pumped lasers and so on. In this study, the in-situ Boron and Phosphorous doping of SiGeSn was investigated, building upon recent studies on in-situ B or P doped GeSn. The surfaces of intrinsic and lowly doped pseudomorphic SiGeSn layers were rough. By contrast, a <110> cross hatch was recovered and surfaces as smooth as the Ge Strain-Relaxed Buffers underneath were obtained for the highest B2H6 or PH3 mass-flows. The surface Root Mean Square roughness and Zrange values were then as low as 0.36 nm and 2.86 nm for SiGeSn:B, and 0.47 nm and 4.60 nm for SiGeSn:P. In addition, Si contents as high as 25% were obtained, notably in SiGeSn:B layers. Dopants were almost fully electrically active in those SiGeSn:B and SiGeSn:P layers, with carrier concentrations as high as 2.0x1020 cm-3 and 2.7x1020 cm-3, respectively. For SiGeSn:P, the shortcoming of in-situ doped GeSn:P was overcome, that is the formation of electrically inactive SnmPnV clusters for high PH3 mass-flows. Such electrically active carrier concentrations will be beneficial for (Si)GeSn based devices, but also for all Group-IV based devices with extremely low thermal budget constraints.

Flash Sintered Potassium Sodium Niobate: High-Performance Piezoelectric Ceramics at Low Thermal Budget Processing.

Alternative sintering technologies promise to overcome issues associated with conventional ceramic sintering such as high thermal budgets and CO2 footprint. The sintering process becomes even more relevant for alkali-based piezoelectric ceramics such as K0.5Na0.5NbO3 (KNN) typically fired above 1100 °C for several hours that induces secondary phase formation and, thereby, degrades their electrical characteristics. Here, an ability of KNN ceramics to be of high performance is successfully demonstrated, using an electric field- and current-assisted Flash sintering technique at 900 °C only. Reported for the first time, Flash sintered KNN ceramics have room-temperature remnant polarization Pr = 21 μC/cm2 and longitudinal piezoelectric coefficient d33 = 117 pC/N, slightly superior to that of conventional ones due to the reduced content of secondary phases. High-performance KNN ceramics Flash sintered at a low-thermal budget have implications for the development of innovative low carbon technologies, electroceramics stakeholders, and piezoelectric energy harvesters.

Low Thermal Budget Growth of Near‐Isotropic Diamond Grains for Heat Spreading in Semiconductor Devices

AbstractThe ever‐increasing power density is a major trend for electronics applications from dense computing to 5G/6G networks. Joule heating and resulting high temperature in the device channel due to the increased power density results in performance degradation and premature failure. Diamond integration near the hot spot can spread the heat by increasing the heat transfer coefficient. Diamond is mostly grown at high temperatures (700–1000 °C), which limits its integration with many semiconductor technologies. Here, a high‐quality 400 °C‐diamond by modifying the gas chemistry at different nucleation stages, with a sharp sp3 Raman peak (FWHM≈6.5 cm−1) and high phase purity (97.1%), similar to 700 °C‐diamond (&gt;98%) is demonstrated. An average grain size of 650 nm with a thickness of 790 nm corresponding to an anisotropy ratio of 1.21 at 400 °C close to the best‐reported of 1.12 at 700 °C is achieved. This near‐isotropic diamond exhibits a relatively high thermal conductivity of ≈300 W m−1 K−1 and a thermal boundary resistance as small as only 5 m2K G−1 W−1 (on SiO2 and Si3N4). Achieving such a high‐quality diamond at 400 °C demonstrates the possibility to grow the diamond on a wide range of semiconductors including Si, InP, Ga2O3, SiC, and GaN where SiO2 or its variations, and Si3N4 are commonly used dielectrics.